{"id":20,"date":"2026-01-15T08:00:06","date_gmt":"2026-01-15T08:00:06","guid":{"rendered":"https:\/\/christian-engelmann.de\/?page_id=20"},"modified":"2026-01-15T22:38:50","modified_gmt":"2026-01-15T22:38:50","slug":"peer-reviewed-conference-papers","status":"publish","type":"page","link":"https:\/\/www.christian-engelmann.info\/?page_id=20","title":{"rendered":"Peer-Reviewed Conference Papers"},"content":{"rendered":"<ol>\n<li>Pedro Valero-Lara, Aaron Young, Thomas Naughton, Christian Engelmann, Al Geist, Jeffrey S. Vetter, Keita Teranishi, and William F. Godoy. <b>ChatMPI: LLM-Driven MPI Code Generation for HPC Workloads<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.sca-hpcasia2026.jp\" target=\"www.sca-hpcasia2026.jp\">Supercomputing Asia \/ International Conference on High Performance Computing in the Asia-Pacific Region (SCA\/HPCAsia) 2026<\/a><\/i>, pages 19-30, Osaka, Japan, January 26-29, 2026. <a href=\"http:\/\/www.acm.org\" target=\"www.acm.org\">ACM Press, New York, NY, USA<\/a>. ISBN 979-8-4007-2067-3. DOI <a href=\"http:\/\/dx.doi.org\/10.1145\/3773656.3773659\" target=\"publication\">10.1145\/3773656.3773659<\/a>. Acceptance rate 36.6% (37\/101). <a href=\"javascript:showAbstract('The Message Passing Interface (MPI) standard plays a crucial role in enabling scientific applications for parallel computing and is an essential component in high-performance computing (HPC). However, implementing MPI code manually--especially applying a proper domain decomposition and communication pattern--is a challenging and error-prone task. We present ChatMPI, an AI assistant for MPI parallelization of sequential C codes. In our analysis, we focus on testing six essential HPC workloads, which are based on Basic Linear Algebra Subprograms levels 1, 2, and 3 as well as sparse, stencil, and iterative operations. We analyze the process of creating ChatMPI by using the ChatHPC library. This lightweight large language model (LLM)-based infrastructure enables HPC experts to efficiently create and supervise trustworthy AI capabilities for critical HPC software tasks. We study the data required for training (fine-tuning) ChatMPI to generate parallel codes that not only use MPI syntax correctly but also apply HPC techniques to reduce memory communication and maximize performance by using proper work decomposition. With a relatively small training dataset composed of a few dozen prompts and fewer than 15 minutes of fine-tuning on one node equipped with two NVIDIA H100 GPUs, ChatMPI elevates trustworthiness for MPI code generation of current LLMs (e.g., Code Llama, ChatGPT-4o and ChatGPT 5). Additionally, we evaluate the performance of the MPI codes generated by ChatMPI in comparison with the ones generated by ChatGPT-4o and ChatGPT-5. The codes generated by ChatMPI provide up to a 4x boost in performance by using better problem decomposition, communication patterns, and HPC techniques (e.g., communication avoiding).');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/valero-lara26chatmpi.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"?page_id=55#valero-lara26chatmpi\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Kibaek Kim, Krishnan Raghavan, Olivera Kotevska, Matthieu Dorier, Ravi Madduri, Minseok Ryu, Todd Munson, Rob Ross, Thomas Flynn, Ai Kagawa, Byung-Jun Yoon, Christian Engelmann, and Farzad Yousefian. <b>Privacy-Preserving Federated Learning for Science: Challenges and Research Directions<\/b>. In <i>Proceedings of the <a href=\"http:\/\/ieeebigdata2024.github.io\" target=\"ieeebigdata2024.github.io\">12th IEEE International Conference on Big Data  (BigData) 2024<\/a><\/i>, pages 7849-7853, Washington, DC, USA, December 15-18, 2024. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 979-8-3503-6249-7. ISSN 2639-1589. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/BigData62323.2024.10825853\" target=\"publication\">10.1109\/BigData62323.2024.10825853<\/a>. Acceptance rate 18.5% (122\/661). <a href=\"javascript:showAbstract('This paper discusses the key challenges and future research directions for privacy-preserving federated learning (PPFL), with a focus on its application to large-scale scientific artificial intelligence models, in particular, foundation models (FMs). PPFL enables collaborative model training across distributed datasets while preserving privacy an important collaborative approach for science. We discuss the need for efficient and scalable algorithms to address the increasing complexity of FMs, particularly when dealing with heterogeneous clients. In addition, we underscore the need for developing advance privacy-preserving techniques, such as differential privacy, to balance privacy and utility in large FMs emphasizing fairness and incentive mechanisms to ensure equitable participation among heterogeneous clients. Finally, we emphasize the need for a robust software stack supporting scalable and secure PPFL deployments across multiple high-performance computing facilities. We envision that PPFL would play a crucial role to advance scientific discovery and enable large-scale, privacy-aware collaborations across science domains.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/kim24privacy.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"?page_id=55#kim24privacy\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Vladyslav Oles, Anna Schmedding, George Ostrouchov, Woong Shi, Evgenia Smirni, and Christian Engelmann. <b>Understanding GPU Memory Corruption at Extreme Scale: The Summit Case Study<\/b>. In <i>Proceedings of the <a href=\"http:\/\/ics2024.github.io\" target=\"ics2024.github.io\">38th ACM International Conference on Supercomputing  (ICS) 2024<\/a><\/i>, pages 188-200, Kyoto, Japan, June 4-7, 2024. <a href=\"http:\/\/www.acm.org\" target=\"www.acm.org\">ACM Press, New York, NY, USA<\/a>. ISBN 979-8-4007-0610-3. DOI <a href=\"http:\/\/dx.doi.org\/10.1145\/3650200.3656615\" target=\"publication\">10.1145\/3650200.3656615<\/a>. Acceptance rate 36.0% (45\/125). <a href=\"publications\/oles24understanding.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/oles24understanding.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#oles24understanding\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann and Suhas Somnath. <b>Science Use Case Design Patterns for Autonomous Experiments<\/b>. In <i>Proceedings of the <a href=\"http:\/\/europlop.net\" target=\"europlop.net\">28th European Conference on Pattern Languages of Programs (EuroPLoP) 2023<\/a><\/i>, pages 1-14, Kloster Irsee, Germany, July 5-9, 2023. <a href=\"http:\/\/www.acm.org\" target=\"www.acm.org\">ACM Press, New York, NY, USA<\/a>. ISBN 979-8-4007-0040-8. DOI <a href=\"http:\/\/dx.doi.org\/10.1145\/3628034.3628060\" target=\"publication\">10.1145\/3628034.3628060<\/a>. <a href=\"javascript:showAbstract('Connecting scientific instruments and robot-controlled laboratories with computing and data resources at the edge, the Cloud or the high-performance computing (HPC) center enables autonomous experiments, self-driving laboratories, smart manufacturing, and artificial intelligence (AI)-driven design, discovery and evaluation. The Self-driven Experiments for Science \/ Interconnected Science Ecosystem (INTERSECT) Open Architecture enables science break- throughs using intelligent networked systems, instruments and facilities with a federated hardware\/software architecture for the laboratory of the future. It relies on a novel approach, consisting of (1) science use case design patterns, (2) a system of systems architecture, and (3) a microservice architecture. This paper introduces the science use case design patterns of the INTERSECT Architecture. It describes the overall background, the involved terminology and concepts, and the pattern format and classification. It further offers an overview of the 12 defined patterns and 4 examples of patterns of 2 different pattern classes. It also provides insight into building solutions from these patterns. The target audience are computer, computational, instrument and domain science experts working in the field of autonomous experiments.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann23science.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"?page_id=55#engelmann23science\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann, Olga Kuchar, Swen Boehm, Michael J. Brim, Thomas Naughton, Suhas Somnath, Scott Atchley, Jack Lange, Ben Mintz, and Elke Arenholz. <b>The INTERSECT Open Federated Architecture for the Laboratory of the Future<\/b>. In <i>Communications in Computer and Information Science (CCIS): Accelerating Science and Engineering Discoveries Through Integrated Research Infrastructure for Experiment, Big Data, Modeling and Simulation. <a href=\"http:\/\/smc.ornl.gov\" target=\"smc.ornl.gov\">18th Smoky Mountains Computational Sciences &#038; Engineering Conference (SMC) 2022<\/a><\/i>, pages 173-190, August 24-25, 2022. <a href=\"http:\/\/www.springer.com\" target=\"www.springer.com\">Springer, Cham<\/a>. ISBN 978-3-031-23605-1. DOI <a href=\"http:\/\/dx.doi.org\/10.1007\/978-3-031-23606-8_11\" target=\"publication\">10.1007\/978-3-031-23606-8_11<\/a>. Acceptance rate 32.4% (24\/74). <a href=\"javascript:showAbstract('A federated instrument-to-edge-to-center architecture is needed to autonomously collect, transfer, store, process, curate, and archive scientific data and reduce human-in-the-loop needs with (a) common interfaces to leverage community and custom software, (b) pluggability to permit adaptable solutions, reuse, and digital twins, and (c) an open standard to enable adoption by science facilities world-wide. The INTERSECT Open Architecture enables science breakthroughs using intelligent networked systems, instruments and facilities with autonomous experiments, &amp;#34;self-driving&amp;#34; laboratories, smart manufacturing and \\glsAI driven design, discovery and evaluation. It creates an open federated architecture for the laboratory of the future using a novel approach, consisting of (1) science use case design patterns, (2) a system of systems architecture, and (3) a microservice architecture.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann22intersect.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/engelmann22intersect.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann22intersect\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Saurabh Hukerikar and Christian Engelmann. <b>PLEXUS: A Pattern-Oriented Runtime System Architecture for Resilient Extreme-Scale High-Performance Computing Systems<\/b>. In <i>Proceedings of the <a href=\"http:\/\/prdc.dependability.org\/PRDC2020\" target=\"prdc.dependability.org\/PRDC2020\">25th IEEE Pacific Rim International Symposium on  Dependable Computing (PRDC) 2020<\/a><\/i>, pages 31-39, Perth, Australia, December 1-4, 2020. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-1-7281-8004-5. ISSN 1555-094X. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/PRDC50213.2020.00014\" target=\"publication\">10.1109\/PRDC50213.2020.00014<\/a>. Acceptance rate 40.9% (18\/44). <a href=\"javascript:showAbstract('For high-performance computing (HPC) system designers and users, meeting the myriad challenges of next-generation exascale supercomputing systems requires rethinking their approach to application and system software design. Among these challenges, providing resiliency and stability to the scientific applications in the presence of high fault rates requires new approaches to software architecture and design. As HPC systems become increasingly complex, they require intricate solutions for detection and mitigation for various modes of faults and errors that occur in these large-scale systems, as well as solutions for failure recovery. These resiliency solutions often interact with and affect other system properties, including application scalability, power and energy efficiency. Therefore, resilience solutions for HPC systems must be thoughtfully engineered and deployed. In previous work, we developed the concept of resilience design patterns, which consist of templated solutions based on well-established techniques for detection, mitigation and recovery. In this paper, we use these patterns as the foundation to propose new approaches to designing runtime systems for HPC systems. The instantiation of these patterns within a runtime system enables flexible and adaptable end-to-end resiliency solutions for HPC environments. The paper describes the architecture of the runtime system, named Plexus, and the strategies for dynamically composing and adapting pattern instances under runtime control. This runtime-based approach enables actively balancing the cost-benefit trade-off between performance overhead and protection coverage of the resilience solutions. Based on a prototype implementation of PLEXUS, we demonstrate the resiliency and performance gains achieved by the pattern-based runtime system for a parallel linear solver application.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/hukerikar20plexus.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"?page_id=55#hukerikar20plexus\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>George Ostrouchov, Don Maxwell, Rizwan Ashraf, Christian Engelmann, Mallikarjun Shankar, and James Rogers. <b>GPU Lifetimes on Titan Supercomputer: Survival Analysis and Reliability<\/b>. In <i>Proceedings of the <a href=\"http:\/\/sc20.supercomputing.org\" target=\"sc20.supercomputing.org\">33rd IEEE\/ACM International Conference on High Performance Computing, Networking, Storage and Analysis (SC) 2020<\/a><\/i>, pages 41:1-14, Atlanta, GA, USA, November 15-20, 2020. <a href=\"http:\/\/www.acm.org\" target=\"www.acm.org\">ACM Press, New York, NY, USA<\/a>. ISBN 9781728199986. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/SC41405.2020.00045\" target=\"publication\">10.1109\/SC41405.2020.00045<\/a>. Acceptance rate 25.1% (95\/378). <a href=\"javascript:showAbstract('The Cray XK7 Titan was the top supercomputer system in the world for a very long time and remained critically important throughout its nearly seven year life. It was also a very interesting machine from a reliability viewpoint as most of its power came from 18,688 GPUs whose operation was forced to execute three very significant rework cycles, two on the GPU mechanical assembly and one on the GPU circuitboards. We write about the last rework cycle and a reliability analysis of over 100,000 operation years in the GPU lifetimes, which correspond to Titan&amp;#39;s 6 year long productive period after an initial break-in period. Using time between failures analysis and statistical survival analysis techniques, we find that GPU reliability is dependent on heat dissipation to an extent that strongly correlates with detailed nuances of the system cooling architecture and job scheduling. In addition to describing some of the system history, the data collection, data cleaning, and our analysis of the data, we provide reliability recommendations for designing future state of the art supercomputing systems and their operation. We make the data and our analysis codes publicly available.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/ostrouchov20gpu.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/ostrouchov20gpu.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#ostrouchov20gpu\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Haewon Jeong, Yaoqing Yang, Christian Engelmann, Vipul Gupta, Tze Meng Low, Pulkit Grover, Viveck Cadambe, and Kannan Ramchandran. <b>3D Coded SUMMA: Communication-Efficient and Robust Parallel Matrix Multiplication<\/b>. In <i>Lecture Notes in Computer Science: Proceedings of the <a href=\"http:\/\/www.euro-par.org\" target=\"www.euro-par.org\">26th European Conference on Parallel and Distributed Computing (Euro-Par) 2020<\/a><\/i>, pages 392-407, Warsaw, Poland, August 24-28, 2020. <a href=\"http:\/\/www.springer.com\" target=\"www.springer.com\">Springer Verlag, Berlin, Germany<\/a>. ISBN 978-3-030-57674-5. DOI <a href=\"http:\/\/dx.doi.org\/10.1007\/978-3-030-57675-2_25\" target=\"publication\">10.1007\/978-3-030-57675-2_25<\/a>. Acceptance rate 24.5% (39\/159). <a href=\"javascript:showAbstract('In this paper, we propose a novel fault-tolerant parallel matrix multiplication algorithm called 3D Coded SUMMA that is communication efficient and achieves higher failure-tolerance than replication-based schemes for the same amount of redundancy. This work bridges the gap between recent developments in coded computing and fault-tolerance in high-performance computing (HPC). The core idea of coded computing is the same as algorithm-based fault-tolerance (ABFT), which is weaving redundancy in the computation using error-correcting codes. In particular, we show that MatDot codes, an innovative code construction for distributed matrix multiplications, can be integrated into three-dimensional SUMMA (Scalable Universal Matrix Multiplication Algorithm) in a communication-avoiding manner. To tolerate any two node failures, the proposed 3D Coded SUMMA requires 50% less redundancy than replication, while the overhead in execution time is only about 5-10%.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/jeong203d.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/jeong203d.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#jeong203d\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Mohit Kumar, Saurabh Gupta, Tirthak Patel, Michael Wilder, Weisong Shi, Song Fu, Christian Engelmann, and Devesh Tiwari. <b>Understanding and Analyzing Interconnect Errors and Network Congestion on a Large Scale HPC System<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.dsn.org\" target=\"www.dsn.org\">48th IEEE\/IFIP International Conference on Dependable  Systems and Networks (DSN) 2018<\/a><\/i>, pages 107-114, Luxembourg City, Luxembourg, June 25-28, 2018. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-1-5386-5596-2. ISSN 2158-3927. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/DSN.2018.00023\" target=\"publication\">10.1109\/DSN.2018.00023<\/a>. Acceptance rate 27.2% (62\/228). <a href=\"javascript:showAbstract('Today&amp;#39;s High Performance Computing (HPC) systems are capable of delivering performance in the order of petaflops due to the fast computing devices, network interconnect, and back-end storage systems. In particular, interconnect resilience and congestion resolution methods have a major impact on the overall interconnect and application performance. This is especially true for scientific applications running multiple processes on different compute nodes as they rely on fast network messages to communicate and synchronize frequently. Unfortunately, the HPC community lacks state-of-practice experience reports that detail how different interconnect errors and congestion events occur on large-scale HPC systems. Therefore, in this paper, we process and analyze interconnect data of the Titan supercomputer to develop a thorough understanding of interconnects faults, errors and congestion events. We also study the interaction between interconnect, errors, network congestion and application characteristics.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/kumar18understanding.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"?page_id=55#kumar18understanding\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Bin Nie, Ji Xue, Saurabh Gupta, Tirthak Patel, Christian Engelmann, Evgenia Smirni, and Devesh Tiwari. <b>Machine Learning Models for GPU Error Prediction in a Large Scale HPC System<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.dsn.org\" target=\"www.dsn.org\">48th IEEE\/IFIP International Conference on Dependable  Systems and Networks (DSN) 2018<\/a><\/i>, pages 95-106, Luxembourg City, Luxembourg, June 25-28, 2018. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-1-5386-5596-2. ISSN 2158-3927. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/DSN.2018.00022\" target=\"publication\">10.1109\/DSN.2018.00022<\/a>. Acceptance rate 27.2% (62\/228). <a href=\"javascript:showAbstract('Recently, GPUs have been widely deployed on large-scale HPC systems to provide powerful computational capability for scientific applications from various domains. As those applications are normally long-running, investigating the characteristics of GPU errors becomes imperative. Therefore, in this paper, we firstly study the conditions that trigger GPU errors with six-month trace data collected from a large-scale operational HPC system. Then, we resort to machine learning techniques to predict the occurrence of GPU errors, by taking advantage of the temporal and spatial dependency of the collected data. As discussed in the evaluation section, the prediction framework is robust and accurate under different workloads.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/nie18machine.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"?page_id=55#nie18machine\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Rizwan Ashraf, Saurabh Hukerikar, and Christian Engelmann. <b>Pattern-based Modeling of Multiresilience Solutions for High-Performance Computing<\/b>. In <i>Proceedings of the <a href=\"http:\/\/icpe2018.spec.org\" target=\"icpe2018.spec.org\">9th ACM\/SPEC International Conference on Performance Engineering (ICPE) 2018<\/a><\/i>, pages 80-87, Berlin, Germany, April 9-13, 2018. <a href=\"http:\/\/www.acm.org\" target=\"www.acm.org\">ACM Press, New York, NY, USA<\/a>. ISBN 978-1-4503-5095-2. DOI <a href=\"http:\/\/dx.doi.org\/10.1145\/3184407.3184421\" target=\"publication\">10.1145\/3184407.3184421<\/a>. Acceptance rate 23.7% (14\/59). <a href=\"javascript:showAbstract('Resiliency is the ability of large-scale high-performance computing (HPC) applications to gracefully handle different types of errors, and recover from failures. In this paper, we propose a pattern-based approach to constructing multiresilience solutions. Using resilience patterns, we evaluate the performance and reliability characteristics of detection, containment and mitigation techniques for transient errors that cause silent data corruptions and techniques for fail-stop errors that result in process failures. We demonstrate the design and implementation of the resilience techniques across multiple layers of the system stack such that they are integrated to work together to achieve resiliency to different error types in a highly performance-effcient manner.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/ashraf18pattern-based.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/ashraf18pattern-based.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#ashraf18pattern-based\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Rizwan Ashraf, Saurabh Hukerikar, and Christian Engelmann. <b>Shrink or Substitute: Handling Process Failures in HPC Systems using In-situ Recovery<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.pdp2018.org\" target=\"www.pdp2018.org\">26th Euromicro International Conference on Parallel, Distributed, and network-based Processing (PDP) 2018<\/a><\/i>, pages 178-185, Cambridge, UK, March 21-23, 2018. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-1-5386-4975-6. ISSN 2377-5750. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/PDP2018.2018.00032\" target=\"publication\">10.1109\/PDP2018.2018.00032<\/a>. Acceptance rate 29.3% (27\/92). <a href=\"javascript:showAbstract('Efficient utilization of today&amp;#39;s high-performance computing (HPC) systems with many, complex software and hardware components requires that the HPC applications are designed to tolerate process failures at runtime. With low mean-time-to-failure (MTTF) of current and future HPC systems, long running simulations on these systems requires capabilities for gracefully handling process failures by the applications themselves. In this paper, we explore the use of fault tolerance extensions to Message Passing Interface (MPI) called user-level failure mitigation (ULFM) for handling process failures without the need to discard the progress made by the application. We explore two alternative recovery strategies, which use ULFM along with application-driven in-memory checkpointing. In the first case, the application is recovered with only the surviving processes, and in the second case, spares are used to replace the failed processes, such that the original configuration of the application is restored. Our experimental results demonstrate that graceful degradation is a viable alternative for recovery in environments where spares may not be available.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/ashraf18shrink.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/ashraf18shrink.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#ashraf18shrink\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Saurabh Gupta, Tirthak Patel, Christian Engelmann, and Devesh Tiwari. <b>Failures in Large Scale Systems: Long-term Measurement, Analysis, and Implications<\/b>. In <i>Proceedings of the <a href=\"http:\/\/sc17.supercomputing.org\" target=\"sc17.supercomputing.org\">30th IEEE\/ACM International Conference on High Performance Computing, Networking, Storage and Analysis (SC) 2017<\/a><\/i>, pages 44:1-44:12, Denver, CO, USA, November 12-17, 2017. <a href=\"http:\/\/www.acm.org\" target=\"www.acm.org\">ACM Press, New York, NY, USA<\/a>. ISBN 978-1-4503-5114-0. DOI <a href=\"http:\/\/dx.doi.org\/10.1145\/3126908.3126937\" target=\"publication\">10.1145\/3126908.3126937<\/a>. Acceptance rate 18.7% (61\/327). <a href=\"javascript:showAbstract('Resilience is one of the key challenges in maintaining high efficiency of future extreme scale supercomputers. Unfortunately, field-data based reliability studies are far in between and not exhaustive. Most HPC researchers and system practitioners still rely on outdated studies to understand HPC reliability characteristics and plan for future HPC systems. While the complexity of managing system reliability has increased, the public knowledge sharing about lessons learned from HPC centers has not increased in the same proportion. To bridge this gap, in this work, we compare and contrast the reliability characteristics of multiple large-scale HPC production systems, and discuss new take-aways and con rm previous findings which continue to be valid.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/gupta17failures.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/gupta17failures.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#gupta17failures\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Bin Nie, Ji Xue, Saurabh Gupta, Christian Engelmann, Evgenia Smirni, and Devesh Tiwari. <b>Characterizing Temperature, Power, and Soft-Error Behaviors in Data Center Systems: Insights, Challenges, and Opportunities<\/b>. In <i>Proceedings of the <a href=\"http:\/\/mascots2017.cs.ucalgary.ca\" target=\"mascots2017.cs.ucalgary.ca\">25th IEEE International Symposium on the Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS) 2017<\/a><\/i>, pages 22-31, Banff, AB, Canada, September 20-22, 2017. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-1-5386-2764-8. ISSN 2375-0227. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/MASCOTS.2017.12\" target=\"publication\">10.1109\/MASCOTS.2017.12<\/a>. Acceptance rate 30.95% (26\/84). <a href=\"javascript:showAbstract('GPUs have become part of the mainstream high performance computing facilities that increasingly require more computational power to simulate physical phenomena quickly and accurately. However, GPU nodes also consume significantly more power than traditional CPU nodes, and high power consumption introduces new system operation challenges, including increased temperature, power\/cooling cost, and lower system reliability. This paper explores how power consumption and temperature characteristics affect reliability, provides insights into what are the implications of such understanding, and how to exploit these insights toward predicting GPU errors using neural networks.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/nie17characterizing.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"?page_id=55#nie17characterizing\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Saurabh Hukerikar and Christian Engelmann. <b>A Pattern Language for High-Performance Computing Resilience<\/b>. In <i>Proceedings of the <a href=\"http:\/\/europlop.net\" target=\"europlop.net\">22nd European Conference on Pattern Languages of Programs (EuroPLoP) 2017<\/a><\/i>, pages 12:1-12:16, Kloster Irsee, Germany, July 12-16, 2017. <a href=\"http:\/\/www.acm.org\" target=\"www.acm.org\">ACM Press, New York, NY, USA<\/a>. ISBN 978-1-4503-4848-5. DOI <a href=\"http:\/\/dx.doi.org\/10.1145\/3147704.3147718\" target=\"publication\">10.1145\/3147704.3147718<\/a>. <a href=\"javascript:showAbstract('High-performance computing systems (HPC) provide powerful capabilities for modeling and simulation, and data analytics in a broad class of computational problems in a variety of scientific and engineering domains. HPC designs are undergoing rapid changes in the hardware architectures and the software environment as the community pursues increasingly capable HPC systems. Among the key challenges for future generations of HPC systems is the ensuring efficient and correct operation despite the occurrence of faults or defects in system components that can cause errors and failures in a HPC system. Such events affect the correctness of the scientific applications, or may lead to their untimely termination. Future generations of HPC systems will consist of millions of compute, memory and storage components and the growing complexity of these computing behemoths increases the chances that a single fault event will cascade across the machine and bring down the entire system. Design patterns capture the essential techniques that are employed to solve recurring problems in the design of resilient computing systems. However, the complexity of modern HPC systems as well as the various challenges of future generations of systems requires consideration to numerous aspects and optimization principles, such as the impact of a resilience solution on the performance and power consumption. We present a pattern language for engineering resilience solutions. The language is targeted at hardware and software designers as well as the users and operators of HPC systems. The patterns are intended to develop complete resilience solutions that have different efficiency and complexity characteristics, which may be deployed at design time or runtime to ensure that HPC systems are able to deal with various types of faults, errors and failures.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/hukerikar17pattern.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"?page_id=55#hukerikar17pattern\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Mahesh Lagadapati, Frank Mueller, and Christian Engelmann. <b>Benchmark Generation and Simulation at Extreme Scale<\/b>. In <i>Proceedings of the <a href=\"http:\/\/ds-rt.com\/2016\" target=\"ds-rt.com\/2016\">20th IEEE\/ACM International Symposium on Distributed Simulation and Real Time Applications (DS-RT) 2016<\/a><\/i>, pages 9-18, London, UK, September 21-23, 2016. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-1-5090-3506-9. ISSN 1550-6525. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/DS-RT.2016.18\" target=\"publication\">10.1109\/DS-RT.2016.18<\/a>. Acceptance rate 42.0% (21\/50). Best paper candidate. <a href=\"javascript:showAbstract('The path to extreme scale high-performance computing (HPC) poses several challenges related to power, performance, resilience, productivity, programmability, data movement, and data management. Investigating the performance of parallel applications at scale on future architectures and the performance impact of different architectural choices is an important component of HPC hardware\/software co-design. Simulations using models of future HPC systems and communication traces from applications running on existing HPC systems can offer an insight into the performance of future architectures. This work targets technology developed for scalable application tracing of communication events. It focuses on extreme-scale simulation of HPC applications and their communication behavior via lightweight parallel discrete event simulation for performance estimation and evaluation. Instead of simply replaying a trace within a simulator, this work promotes the generation of a benchmark from traces. This benchmark is subsequently exposed to simulation using models to reflect the performance characteristics of future-generation HPC systems. This technique provides a number of benefits, such as eliminating the data intensive trace replay and enabling simulations at different scales. The presented work features novel software co-design aspects, combining the ScalaTrace tool to generate scalable trace files, the ScalaBenchGen tool to generate the benchmark, and the xSim tool to assess the benchmark characteristics within a simulator.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/lagadapati16benchmark.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/lagadapati16benchmark.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#lagadapati16benchmark\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Saurabh Hukerikar and Christian Engelmann. <b>Havens: Explicit Reliable Memory Regions for HPC Applications<\/b>. In <i>Proceedings of the <a href=\"http:\/\/ieee-hpec.org\" target=\"ieee-hpec.org\">20th IEEE High Performance Extreme Computing Conference (HPEC) 2016<\/a><\/i>, pages 1-6, Waltham, MA, USA, September 13-15, 2016. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/HPEC.2016.7761593\" target=\"publication\">10.1109\/HPEC.2016.7761593<\/a>. <a href=\"javascript:showAbstract('Supporting error resilience in future exascale-class supercomputing systems is a critical challenge. Due to transistor scaling trends and increasing memory density, the scientific simulations are expected to experience more interruptions caused by soft errors in the system memory. Existing hardware-based detection and recovery techniques will be inadequate in the presence of high memory fault rates. In this paper we propose a partial memory protection scheme using region-based memory management. We define regions called havens that provide fault protection for program objects. We provide reliability for the regions through a software-based parity protection mechanism. Our approach enables critical application code and variables to be placed in these havens. The fault coverage of our approach is application agnostic unlike algorithm-based fault tolerance techniques.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/hukerikar16havens.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/hukerikar16havens.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#hukerikar16havens\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Kun Tang, Devesh Tiwari, Saurabh Gupta, Ping Huang, QiQi Lu, Christian Engelmann, and Xubin He. <b>Power-Capping Aware Checkpointing: On the Interplay Among Power-Capping, Temperature, Reliability, Performance, and Energy<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.dsn.org\" target=\"www.dsn.org\">46th IEEE\/IFIP International Conference on Dependable  Systems and Networks (DSN) 2016<\/a><\/i>, pages 311-322, Toulouse, France, June 28 &#8211; July 1, 2016. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISSN 2158-3927. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/DSN.2016.36\" target=\"publication\">10.1109\/DSN.2016.36<\/a>. Acceptance rate 22.4% (58\/259). <a href=\"javascript:showAbstract('Checkpoint and restart mechanisms have been widely used in large scientific simulation applications to make forward progress in case of failures. However, none of the prior works have considered the interaction of power-constraint with temperature, reliability, performance, and checkpointing interval. It is not clear how power-capping may affect optimal checkpointing interval. What are the involved reliability, performance, and energy trade-offs? In this paper, we develop a deep understanding about the interaction between power-capping and scientific applications using checkpoint\/restart as resilience mechanism, and propose a new model for the optimal checkpointing interval (OCI) under power-capping. Our study reveals several interesting, and previously unknown, insights about how power-capping affects the reliability, energy consumption, performance.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/tang16power-capping.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"?page_id=55#tang16power-capping\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>David Fiala, Frank Mueller, Kurt Ferreira, and Christian Engelmann. <b>Mini-Ckpts: Surviving OS Failures in Persistent Memory<\/b>. In <i>Proceedings of the <a href=\"http:\/\/ics16.bilkent.edu.tr\" target=\"ics16.bilkent.edu.tr\">30th ACM International Conference on Supercomputing  (ICS) 2016<\/a><\/i>, pages 7:1-7:14, Istanbul, Turkey, June 1-3, 2016. <a href=\"http:\/\/www.acm.org\" target=\"www.acm.org\">ACM Press, New York, NY, USA<\/a>. ISBN 978-1-4503-4361-9. DOI <a href=\"http:\/\/dx.doi.org\/10.1145\/2925426.2926295\" target=\"publication\">10.1145\/2925426.2926295<\/a>. Acceptance rate 24.2% (43\/178). <a href=\"javascript:showAbstract('Concern is growing in the high-performance computing (HPC) community on the reliability of future extreme-scale systems. Current efforts have focused on application fault-tolerance rather than the operating system (OS), despite the fact that recent studies have suggested that failures in OS memory are more likely. The OS is critical to a system&amp;#39;s correct and efficient operation of the node and processes it governs -- and in HPC also for any other nodes a parallelized application runs on and communicates with: Any single node failure generally forces all processes of this application to terminate due to tight communication in HPC. Therefore, the OS itself must be capable of tolerating failures. In this work, we introduce mini-ckpts, a framework which enables application survival despite the occurrence of a fatal OS failure or crash. Mini-ckpts achieves this tolerance by ensuring that the critical data describing a process is preserved in persistent memory prior to the failure. Following the failure, the OS is rejuvenated via a warm reboot and the application continues execution effectively making the failure and restart transparent. The mini-ckpts rejuvenation and recovery process is measured to take between three to six seconds and has a failure-free overhead of between 3-5% for a number of key HPC workloads. In contrast to current fault-tolerance methods, this work ensures that the operating and runtime system can continue in the presence of faults. This is a much finer-grained and dynamic method of fault-tolerance than the current, coarse-grained, application-centric methods. Handling faults at this level has the potential to greatly reduce overheads and enables mitigation of additional fault scenarios.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/fiala16mini-ckpts.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/fiala16mini-ckpts.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#fiala16mini-ckpts\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Leonardo Bautista-Gomez, Ana Gainaru, Swann Perarnau, Devesh Tiwari, Saurabh Gupta, Franck Cappello, Christian Engelmann, and Marc Snir. <b>Reducing Waste in Extreme Scale Systems Through Introspective Analysis<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.ipdps.org\" target=\"www.ipdps.org\">30th IEEE International Parallel and Distributed Processing Symposium (IPDPS) 2016<\/a><\/i>, pages 212-221, Chicago, IL, USA, May 23-27, 2016. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISSN 1530-2075. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/IPDPS.2016.100\" target=\"publication\">10.1109\/IPDPS.2016.100<\/a>. Acceptance rate 23.0% (114\/496). <a href=\"javascript:showAbstract('Resilience is an important challenge for extreme-scale  supercomputers. Today, failures in supercomputers are  assumed to be uniformly distributed in time. However, recent  studies show that failures in high-performance computing  systems are partially correlated in time, generating periods  of higher failure density. Our study of the failure logs of  multiple supercomputers show that periods of higher failure  density occur with up to three times more than the average.  We design a monitoring system that listens to hardware  events and forwards important events to the runtime to  detect those regime changes. We implement a runtime capable  of receiving notifications and adapt dynamically. In  addition, we build an analytical model to predict the gains  that such dynamic approach could achieve. We demonstrate that  in some systems, our approach can reduce the wasted time.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/bautista-gomez16reducing.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/bautista-gomez16reducing.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#bautista-gomez16reducing\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann and Thomas Naughton. <b>Supporting the Development of Soft-Error Resilient Message Passing Applications using Simulation<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.iasted.org\/conferences\/home-795.html\" target=\"www.iasted.org\/conferences\/home-795.html\">13th IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN) 2016<\/a><\/i>, Innsbruck, Austria, February 15-16, 2016. <a href=\"http:\/\/www.actapress.com\" target=\"www.actapress.com\">ACTA Press, Calgary, AB, Canada<\/a>. ISBN 978-0-88986-979-0. DOI <a href=\"http:\/\/dx.doi.org\/10.2316\/P.2016.834-005\" target=\"publication\">10.2316\/P.2016.834-005<\/a>. <a href=\"javascript:showAbstract('Radiation-induced bit flip faults are of particular concern in extreme-scale high-performance computing systems. This paper presents a simulation-based tool that enables the development of soft-error resilient message passing applications by permitting the investigation of their correctness and performance under various fault conditions. The documented extensions to the Extreme-scale Simulator (xSim) enable the injection of bit flip faults at specific of injection location(s) and fault activation time(s), while supporting a significant degree of configurability of the fault type. Experiments show that the simulation overhead with the new feature is ~2,325% for serial execution and ~1,730% at 128 MPI processes, both with very fine-grain fault injection. Fault injection experiments demonstrate the usefulness of the new feature by injecting bit flips in the input and output matrices of a matrix-matrix multiply application, revealing vulnerability of data structures, masking and error propagation. xSim is the very first simulation-based MPI performance tool that supports both, the injection of process failures and bit flip faults.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann16supporting.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/engelmann16supporting.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann16supporting\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Amogh Katti, Giuseppe Di Fatta, Thomas Naughton, and Christian Engelmann. <b>Scalable and Fault Tolerant Failure Detection and Consensus<\/b>. In <i>Proceedings of the <a href=\"http:\/\/eurompi2015.bordeaux.inria.fr\" target=\"eurompi2015.bordeaux.inria.fr\">22nd European MPI Users` Group Meeting (EuroMPI) 2015<\/a><\/i>, pages 13:1-13:9, Bordeaux, France, September 21-24, 2015. <a href=\"http:\/\/www.acm.org\" target=\"www.acm.org\">ACM Press, New York, NY, USA<\/a>. ISBN 978-1-4503-3795-3. DOI <a href=\"http:\/\/dx.doi.org\/10.1145\/2802658.2802660\" target=\"publication\">10.1145\/2802658.2802660<\/a>. Acceptance rate 48.3% (14\/29). <a href=\"javascript:showAbstract('Future extreme-scale high-performance computing systems will be required to work under frequent component failures. The MPI Forum&amp;#39;s User Level Failure Mitigation proposal has introduced an operation (MPI_Comm_shrink) to synchronize the alive processes on the list of failed processes, so that applications can continue to execute even in the presence of failures by adopting algorithm-based fault tolerance techniques. The MPI_Comm_shrink operation requires a fault tolerant failure detection and consensus algorithm. This paper presents and compares two novel failure detection and consensus algorithms to support this operation. The proposed algorithms are based on Gossip protocols and are inherently fault-tolerant and scalable. The proposed algorithms were implemented and tested using the Extreme-scale Simulator. The results show that in both algorithms the number of Gossip cycles to achieve global consensus scales logarithmically with system size. The second algorithm also shows better scalability in terms of memory usage and network bandwidth costs and a perfect synchronization in achieving global consensus.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/katti15scalable.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/katti15scalable.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#katti15scalable\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann and Thomas Naughton. <b>A Network Contention Model for the Extreme-scale Simulator<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.iasted.org\/conferences\/home-826.html\" target=\"www.iasted.org\/conferences\/home-826.html\">34th IASTED International Conference on Modelling, Identification and Control (MIC) 2015<\/a><\/i>, Innsbruck, Austria, February 17-18, 2015. <a href=\"http:\/\/www.actapress.com\" target=\"www.actapress.com\">ACTA Press, Calgary, AB, Canada<\/a>. ISBN 978-0-88986-975-2. DOI <a href=\"http:\/\/dx.doi.org\/10.2316\/P.2015.826-043\" target=\"publication\">10.2316\/P.2015.826-043<\/a>. <a href=\"javascript:showAbstract('The Extreme-scale Simulator (xSim) is a performance investigation toolkit for high-performance computing (HPC) hardware\/software co-design. It permits running a HPC application with millions of concurrent execution threads, while observing its performance in a simulated extreme-scale system. This paper details a newly developed network modeling feature for xSim, eliminating the shortcomings of the existing network modeling capabilities. The approach takes a different path for implementing network contention and bandwidth capacity modeling using a less synchronous and accurate enough model design. With the new network modeling feature, xSim is able to simulate on-chip and on-node networks with reasonable accuracy and overheads.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann15network.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/engelmann15network.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann15network\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann and Thomas Naughton. <b>Improving the Performance of the Extreme-scale Simulator<\/b>. In <i>Proceedings of the <a href=\"http:\/\/ds-rt.com\/2014\" target=\"ds-rt.com\/2014\">18th IEEE\/ACM International Symposium on Distributed Simulation and Real Time Applications (DS-RT) 2014<\/a><\/i>, pages 198-207, Toulouse, France, October 1-3, 2014. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-1-4799-6143-6. ISSN 1550-6525. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/DS-RT.2014.32\" target=\"publication\">10.1109\/DS-RT.2014.32<\/a>. Best paper candidate. <a href=\"javascript:showAbstract('Investigating the performance of parallel applications at scale on future high-performance computing (HPC) architectures and the performance impact of different architecture choices is an important component of HPC hardware\/software co-design. The Extreme-scale Simulator (xSim) is a simulation-based toolkit for investigating the performance of parallel applications at scale. xSim scales to millions of simulated Message Passing Interface (MPI) processes. The overhead introduced by a simulation tool is an important performance and productivity aspect. This paper documents two improvements to xSim: (1) a new deadlock resolution protocol to reduce the parallel discrete event simulation management overhead and (2) a new simulated MPI message matching algorithm to reduce the oversubscription management overhead. The results clearly show a significant performance improvement, such as by reducing the simulation overhead for running the NAS Parallel Benchmark suite inside the simulator  from 1,020% to 238% for the conjugate gradient (CG) benchmark and from 102% to 0% for the embarrassingly parallel (EP) and benchmark, as well as, from 37,511% to 13,808% for CG and from 3,332% to 204% for EP with accurate process failure simulation.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann14improving.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/engelmann14improving.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann14improving\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Thomas Naughton, Christian Engelmann, Geoffroy Vall&eacute;e, and Swen B&ouml;hm. <b>Supporting the Development of Resilient Message Passing Applications using Simulation<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.pdp2014.org\" target=\"www.pdp2014.org\">22nd Euromicro International Conference on Parallel, Distributed, and network-based Processing (PDP) 2014<\/a><\/i>, pages 271-278, Turin, Italy, February 12-14, 2014. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISSN 1066-6192. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/PDP.2014.74\" target=\"publication\">10.1109\/PDP.2014.74<\/a>. Acceptance rate 32.6% (73\/224). <a href=\"javascript:showAbstract('An emerging aspect of high-performance computing (HPC) hardware\/software co-design is investigating performance under failure. The work in this paper extends the Extreme-scale Simulator (xSim), which was designed for evaluating the performance of message passing interface (MPI) applications on future HPC architectures, with fault-tolerant MPI extensions proposed by the MPI Fault Tolerance Working Group. xSim permits running MPI applications with millions of concurrent MPI ranks, while observing application performance in a simulated extreme-scale system using a lightweight parallel discrete event simulation. The newly added features offer user-level failure mitigation (ULFM) extensions at the simulated MPI layer to support algorithm-based fault tolerance (ABFT). The presented solution permits investigating performance under failure and failure handling of ABFT solutions. The newly enhanced xSim is the very first performance tool that supports ULFM and ABFT.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/naughton14supporting.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/naughton14supporting.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#naughton14supporting\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Geoffroy Vall&eacute;e, Thomas Naughton, Swen B&ouml;hm, and Christian Engelmann. <b>A Runtime Environment for Supporting Research in Resilient HPC System Software &#038; Tools<\/b>. In <i>Proceedings of the <a href=\"http:\/\/is-candar.org\" target=\"is-candar.org\">1st International Symposium on Computing and Networking &#8211; Across Practical Development and Theoretical Research &#8211; (CANDAR) 2013<\/a><\/i>, pages 213-219, Matsuyama, Japan, December 4-6, 2013. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-1-4799-2795-1. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/CANDAR.2013.38\" target=\"publication\">10.1109\/CANDAR.2013.38<\/a>. Acceptance rate 35.8% (28\/78). <a href=\"javascript:showAbstract('The high-performance computing (HPC) community continues to increase the size and complexity of hardware platforms that support advanced scientific workloads. The runtime environment (RTE) is a crucial layer in the software stack for these large-scale systems. The RTE manages the interface between the operating system and the application running in parallel on the machine. The deployment of applications and tools on large-scale HPC computing systems requires the RTE to manage process creation in a scalable manner, support sparse connectivity, and provide fault tolerance. We have developed a new RTE that provides a basis for building distributed execution environments and developing tools for HPC to aid research in system software and resilience. This paper describes the software architecture of the Scalable runTime Component Infrastructure (STCI), which is intended to provide a complete infrastructure for scalable start-up and management of many processes in large-scale HPC systems. We highlight features of the current implementation, which is provided as a system library that allows developers to easily use and integrate STCI in their tools and\/or applications. The motivation for this work has been to support ongoing research activities in fault-tolerance for large-scale systems. We discuss the advantages of the modular framework employed and describe two use cases that demonstrate its capabilities: (i) an alternate runtime for a Message Passing Interface (MPI) stack, and (ii) a distributed control and communication substrate for a fault-injection tool.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/vallee13runtime.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/vallee13runtime.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#vallee13runtime\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann. <b>Investigating Operating System Noise in Extreme-Scale High-Performance Computing Systems using Simulation<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.iasted.org\/conferences\/home-795.html\" target=\"www.iasted.org\/conferences\/home-795.html\">11th IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN) 2013<\/a><\/i>, Innsbruck, Austria, February 11-13, 2013. <a href=\"http:\/\/www.actapress.com\" target=\"www.actapress.com\">ACTA Press, Calgary, AB, Canada<\/a>. ISBN 978-0-88986-943-1. DOI <a href=\"http:\/\/dx.doi.org\/10.2316\/P.2013.795-010\" target=\"publication\">10.2316\/P.2013.795-010<\/a>. <a href=\"javascript:showAbstract('Hardware\/software co-design for future-generation high-performance computing (HPC) systems aims at closing the gap between the peak capabilities of the hardware and the performance realized by applications (application-architecture performance gap). Performance profiling of architectures and applications is a crucial part of this iterative process. The work in this paper focuses on operating system (OS) noise as an additional factor to be considered for co-design. It represents the first step in including OS noise in HPC hardware\/software co-design by adding a noise injection feature to an existing simulation-based co-design toolkit. It reuses an existing abstraction for OS noise with frequency (periodic recurrence) and period (duration of each occurrence) to enhance the processor model of the Extreme-scale Simulator (xSim) with synchronized and random OS noise simulation. The results demonstrate this capability by evaluating the impact of OS noise on MPI_Bcast() and MPI_Reduce() in a simulated future-generation HPC system with 2,097,152 compute nodes.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann13investigating.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/engelmann13investigating.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann13investigating\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>David Fiala, Frank Mueller, Christian Engelmann, Kurt Ferreira, Ron Brightwell, and Rolf Riesen. <b>Detection and Correction of Silent Data Corruption for Large-Scale High-Performance Computing<\/b>. In <i>Proceedings of the <a href=\"http:\/\/sc12.supercomputing.org\" target=\"sc12.supercomputing.org\">25th IEEE\/ACM International Conference on High Performance Computing, Networking, Storage and Analysis (SC) 2012<\/a><\/i>, pages 78:1-78:12, Salt Lake City, UT, USA, November 10-16, 2012. <a href=\"http:\/\/www.acm.org\" target=\"www.acm.org\">ACM Press, New York, NY, USA<\/a>. ISBN 978-1-4673-0804-5. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/SC.2012.49\" target=\"publication\">10.1109\/SC.2012.49<\/a>. Acceptance rate 21.2% (100\/472). <a href=\"javascript:showAbstract('Faults have become the norm rather than the exception for high-end computing on clusters with 10s\/100s of thousands of cores. Exacerbating this situation, some of these faults remain undetected, manifesting themselves as silent errors that corrupt memory while applications continue to operate and report incorrect results. This paper studies the potential for redundancy to both detect and correct soft errors in MPI message-passing applications. Our study investigates the challenges inherent to detecting soft errors within MPI application while providing transparent MPI redundancy. By assuming a model wherein corruption in application data manifests itself by producing differing MPI message data between replicas, we study the best suited protocols for detecting and correcting MPI data that is the result of corruption. To experimentally validate our proposed detection and correction protocols, we introduce RedMPI, an MPI library which resides in the MPI profiling layer. RedMPI is capable of both online detection and correction of soft errors that occur in MPI applications without requiring any modifications to the application source by utilizing either double or triple redundancy. Our results indicate that our most efficient consistency protocol can successfully protect applications experiencing even high rates of silent data corruption with runtime overheads between 0% and 30% as compared to unprotected applications without redundancy. Using our fault injector within RedMPI, we observe that even a single soft error can have profound effects on running applications, causing a cascading pattern of corruption in most cases causes that spreads to all other processes. RedMPI&amp;#39;s protection has been shown to successfully mitigate the effects of soft errors while allowing applications to complete with correct results even in the face of errors.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/fiala12detection2.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/fiala12detection2.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#fiala12detection2\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>James Elliott, Kishor Kharbas, David Fiala, Frank Mueller, Kurt Ferreira, and Christian Engelmann. <b>Combining Partial Redundancy and Checkpointing for HPC<\/b>. In <i>Proceedings of the <a href=\"http:\/\/icdcs-2012.org\/\" target=\"icdcs-2012.org\/\">32nd International Conference on Distributed Computing Systems (ICDCS) 2012<\/a><\/i>, pages 615-626, Macau, SAR, China, June 18-21, 2012. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-0-7695-4685-8. ISSN 1063-6927. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/ICDCS.2012.56\" target=\"publication\">10.1109\/ICDCS.2012.56<\/a>. Acceptance rate 13.8% (71\/515). <a href=\"javascript:showAbstract('Today&amp;#39;s largest High Performance Computing (HPC) systems exceed one Petaflops (10^15 floating point operations per second) and exascale systems are projected within seven years. But reliability is becoming one of the major challenges faced by exascale computing. With billion-core parallelism, the mean time to failure is projected to be in the range of minutes or hours instead of days. Failures are becoming the norm rather than the exception during execution of HPC applications. Current fault tolerance techniques in HPC focus on reactive ways to mitigate faults, namely via checkpoint and restart (C\/R). Apart from storage overheads, C\/R-based fault recovery comes at an additional cost in terms of application performance because normal execution is disrupted when checkpoints are taken. Studies have shown that applications running at a large scale spend more than 50% of their total time saving checkpoints, restarting and redoing lost work. Redundancy is another fault tolerance technique, which employs redundant processes performing the same task. If a process fails, a replica of it can take over its execution. Thus, redundant copies can decrease the overall failure rate. The downside of redundancy is that extra resources are required and there is an additional overhead on communication and synchronization. This work contributes a model and analyzes the benefit of C\/R in coordination with redundancy at different degrees to minimize the total wallclock time and resources utilization of HPC applications. We further conduct experiments with an implementation of redundancy within the MPI layer on a cluster. Our experimental results confirm the benefit of dual and triple redundancy - but not for partial redundancy - and show a close fit to the model. At 80,000 processes, dual redundancy requires twice the number of processing resources for an application but allows two jobs of 128 hours wallclock time to finish within the time of just one job without redundancy. For narrow ranges of processor counts, partial redundancy results in the lowest time. Once the count exceeds 770, 000, triple redundancy has the lowest overall cost. Thus, redundancy allows one to trade-off additional resource requirements against wallclock time, which provides a tuning knob for users to adapt to resource availabilities.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/elliott12combining.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/elliott12combining.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#elliott12combining\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Chao Wang, Sudharshan S. Vazhkudai, Xiaosong Ma, Fei Meng, Youngjae Kim, and Christian Engelmann. <b>NVMalloc: Exposing an Aggregate SSD Store as a Memory Partition in Extreme-Scale Machines<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.ipdps.org\" target=\"www.ipdps.org\">26th IEEE International Parallel and Distributed Processing Symposium (IPDPS) 2012<\/a><\/i>, pages 957-968, Shanghai, China, May 21-25, 2012. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-0-7695-4675-9. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/IPDPS.2012.90\" target=\"publication\">10.1109\/IPDPS.2012.90<\/a>. Acceptance rate 20.7% (118\/569). <a href=\"javascript:showAbstract('DRAM is a precious resource in extreme-scale machines and is increasingly becoming scarce, mainly due to the growing number of cores per node. On future multi-petaflop and exaflop machines, the memory pressure is likely to be so severe that we need to rethink our memory usage models. Fortunately, the advent of non-volatile memory (NVM) offers a unique opportunity in this space. Current NVM offerings possess several desirable properties, such as low cost and power efficiency, but also suffer from high latency and lifetime issues. We need rich techniques to be able to use them alongside DRAM. In this paper, we propose a novel approach to exploiting NVM as a secondary memory partition so that applications can explicitly allocate and manipulate memory regions therein. More specifically, we propose an NVMalloc library with a suite of services that enables applications to access a distributed NVM storage system. We have devised ways within NVMalloc so that the storage system, built from compute node-local NVM devices, can be accessed in a byte-addressable fashion using the memory mapped I\/O interface. Our approach has the potential to re-energize out-of-core computations on large-scale machines by having applications allocate certain variables through NVMalloc, thereby increasing the overall memory available for the application. Our evaluation on a 128-core cluster shows that NVMalloc enables applications to compute problem sizes larger than the physical memory in a cost-effective manner. It can achieve better performance with increased computation time between NVM memory accesses or increased data access locality. In addition, our results suggest that while NVMalloc enables transparent access to NVM-resident variables, the explicit control it provides is crucial to optimize application performance.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/wang12nvmalloc.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/wang12nvmalloc.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#wang12nvmalloc\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Swen B&ouml;hm and Christian Engelmann. <b>File I\/O for MPI Applications in Redundant Execution Scenarios<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.pdp2012.org\" target=\"www.pdp2012.org\">20th Euromicro International Conference on Parallel, Distributed, and network-based Processing (PDP) 2012<\/a><\/i>, pages 112-119, Garching, Germany, February 15-17, 2012. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-0-7695-4633-9. ISSN 1066-6192. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/PDP.2012.22\" target=\"publication\">10.1109\/PDP.2012.22<\/a>. <a href=\"javascript:showAbstract('As multi-petascale and exa-scale high-performance computing (HPC) systems inevitably have to deal with a number of resilience challenges, such as a significant growth in component count and smaller circuit sizes with lower circuit voltages, redundancy may offer an acceptable level of resilience that traditional fault tolerance techniques, such as checkpoint\/restart, do not. Although redundancy in HPC is quite controversial due to the associated cost for redundant components,  the constantly increasing number of cores-per-processor is tilting this cost calculation toward a system design where computation, such as for redundancy, is much cheaper and communication, needed for checkpoint\/restart, is much more expensive. Recent research and development activities in redundancy for Message Passing Interface (MPI) applications focused on availability\/reliability models and replication algorithms. This paper takes a first step toward solving an open research problem associated with running a parallel application redundantly, which is file I\/O under redundancy. The approach intercepts file I\/O calls made by a redundant application to employ coordination protocols that execute file I\/O operations in a redundancy-oblivious fashion when accessing a node-local file system, or in a redundancy-aware fashion when accessing a shared networked file system. A proof-of concept prototype is presented and a number of coordination protocols are described and evaluated. The results show the performance impact for redundantly accessing a shared networked file system, but also demonstrate the capability to regain performance by utilizing MPI communication between replicas and parallel file I\/O.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/boehm12file.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/boehm12file.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#boehm12file\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Swen B&ouml;hm and Christian Engelmann. <b>xSim: The Extreme-Scale Simulator<\/b>. In <i>Proceedings of the <a href=\"http:\/\/hpcs11.cisedu.info\" target=\"hpcs11.cisedu.info\">International Conference on High Performance Computing and Simulation (HPCS) 2011<\/a><\/i>, pages 280-286, Istanbul, Turkey, July 4-8, 2011. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-1-61284-383-4. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/HPCSim.2011.5999835\" target=\"publication\">10.1109\/HPCSim.2011.5999835<\/a>. Acceptance rate 28.1% (48\/171). <a href=\"javascript:showAbstract('Investigating parallel application performance properties at scale is becoming an important part of high-performance computing (HPC) application development and deployment. The Extreme-scale Simulator (xSim) is a performance investigation toolkit that permits running an application in a controlled environment at extreme scale without the need for a respective extreme-scale HPC system. Using a lightweight parallel discrete event simulation, xSim executes a parallel application with a virtual wall clock time, such that performance data can be extracted based on a processor model and a network model. This paper presents significant enhancements to the xSim toolkit prototype that provide a more complete Message Passing Interface (MPI) support and improve its versatility. These enhancements include full virtual MPI group, communicator and collective communication support, and global variables support. The new capabilities are demonstrated by executing the entire NAS Parallel Benchmark suite in a simulated HPC environment.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/boehm11xsim.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/boehm11xsim.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#boehm11xsim\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann and Swen B&ouml;hm. <b>Redundant Execution of HPC Applications with MR-MPI<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.iasted.org\/conferences\/home-719.html\" target=\"www.iasted.org\/conferences\/home-719.html\">10th IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN) 2011<\/a><\/i>, pages 31-38, Innsbruck, Austria, February 15-17, 2011. <a href=\"http:\/\/www.actapress.com\" target=\"www.actapress.com\">ACTA Press, Calgary, AB, Canada<\/a>. ISBN 978-0-88986-864-9. DOI <a href=\"http:\/\/dx.doi.org\/10.2316\/P.2011.719-031\" target=\"publication\">10.2316\/P.2011.719-031<\/a>. <a href=\"javascript:showAbstract('This paper presents a modular-redundant Message Passing Interface (MPI) solution, MR-MPI, for transparently executing  high-performance computing (HPC) applications in a redundant fashion. The presented work addresses the deficiencies of recovery-oriented HPC, i.e., checkpoint\/restart to\/from a parallel file system, at extreme scale by adding the redundancy approach to the HPC resilience portfolio. It utilizes the MPI performance tool interface, PMPI, to transparently intercept MPI calls from an application and to hide all redundancy-related mechanisms. A redundantly executed application runs with &amp;#36;r*m native MPI processes, where r is the number of MPI ranks visible to the application and m is the replication degree. Messages between redundant nodes are replicated. Partial replication for tunable resilience is supported. The performance results clearly show the negative impact of the O(m^2) messages between replicas. For low-level, point-to-point benchmarks, the impact can be as high as the replication degree. For applications, performance highly depends on the actual communication types and counts. On single-core systems, the overhead can be 0% for embarrassingly parallel applications independent of the employed redundancy configuration or up to 70-90% for communication-intensive applications in a dual-redundant configuration. On multi-core systems, the overhead can be significantly higher due to the additional communication contention.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann11redundant.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/engelmann11redundant.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann11redundant\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Chao Wang, Frank Mueller, Christian Engelmann, and Stephen L. Scott. <b>Hybrid Checkpointing for MPI Jobs in HPC Environments<\/b>. In <i>Proceedings of the <a href=\"http:\/\/grid.sjtu.edu.cn\/icpads10\" target=\"grid.sjtu.edu.cn\/icpads10\">16th IEEE International Conference on Parallel and Distributed Systems (ICPADS) 2010<\/a><\/i>, pages 524-533, Shanghai, China, December 8-10, 2010. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-0-7695-4307-9. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/ICPADS.2010.48\" target=\"publication\">10.1109\/ICPADS.2010.48<\/a>. Acceptance rate 29.6% (77\/188). <a href=\"javascript:showAbstract('As the core count in high-performance computing systems keeps increasing, faults are becoming common place. Check pointing addresses such faults but captures full process images even though only a subset of the process image changes between checkpoints. We have designed a hybrid check pointing technique for MPI tasks of high-performance applications. This technique alternates between full and incremental checkpoints: At incremental checkpoints, only data changed since the last checkpoint is captured. Our implementation integrates new BLCR and LAM\/MPI features that complement traditional full checkpoints. This results in significantly reduced checkpoint sizes and overheads with only moderate increases in restart overhead. After accounting for cost and savings, benefits due to incremental checkpoints are an order of magnitude larger than overheads on restarts. We further derive qualitative results indicating an optimal balance between full\/incremental checkpoints of our novel approach at a ratio of 1:9, which outperforms both always-full and always-incremental check pointing.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/wang10hybrid2.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/wang10hybrid2.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#wang10hybrid2\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Min Li, Sudharshan S. Vazhkudai, Ali R. Butt, Fei Meng, Xiaosong Ma, Youngjae Kim, Christian Engelmann, and Galen Shipman. <b>Functional Partitioning to Optimize End-to-End Performance on Many-Core Architectures<\/b>. In <i>Proceedings of the <a href=\"http:\/\/sc10.supercomputing.org\" target=\"sc10.supercomputing.org\">23rd IEEE\/ACM International Conference on High Performance Computing, Networking, Storage and Analysis (SC) 2010<\/a><\/i>, pages 1-12, New Orleans, LA, USA, November 13-19, 2010. <a href=\"http:\/\/www.acm.org\" target=\"www.acm.org\">ACM Press, New York, NY, USA<\/a>. ISBN 978-1-4244-7559-9. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/SC.2010.28\" target=\"publication\">10.1109\/SC.2010.28<\/a>. Acceptance rate 19.8% (50\/253). <a href=\"javascript:showAbstract('Scaling computations on emerging massive-core supercomputers is a daunting task, which coupled with the significantly lagging system I\/O capabilities exacerbates applications&amp;#39; end-to-end performance. The I\/O bottleneck often negates potential performance benefits of assigning additional compute cores to an application. In this paper, we address this issue via a novel functional partitioning (FP) runtime environment that allocates cores to specific application tasks - checkpointing, de-duplication, and scientific data format transformation - so that the deluge of cores can be brought to bear on the entire gamut of application activities. The focus is on utilizing the extra cores to support HPC application I\/O activities and also leverage solid-state disks in this context. For example, our evaluation shows that dedicating 1 core on an oct-core machine for checkpointing and its assist tasks using FP can improve overall execution time of a FLASH benchmark on 80 and  160 cores by 43.95% and 41.34%, respectively.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/li10functional.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/li10functional.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#li10functional\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Swen B&ouml;hm, Christian Engelmann, and Stephen L. Scott. <b>Aggregation of Real-Time System Monitoring Data for Analyzing Large-Scale Parallel and Distributed Computing Environments<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.anss.org.au\/hpcc2010\" target=\"www.anss.org.au\/hpcc2010\">12th IEEE International Conference on High Performance Computing and Communications (HPCC) 2010<\/a><\/i>, pages 72-78, Melbourne, Australia, September 1-3, 2010. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-0-7695-4214-0. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/HPCC.2010.32\" target=\"publication\">10.1109\/HPCC.2010.32<\/a>. Acceptance rate 19.1% (58\/304). <a href=\"javascript:showAbstract('We present a monitoring system for large-scale parallel and distributed computing environments that allows to trade-off accuracy in a tunable fashion to gain scalability without compromising fidelity. The approach relies on classifying each gathered monitoring metric based on individual needs and on aggregating messages containing classes of individual monitoring metrics using a tree-based overlay network. The MRNet-based prototype is able to significantly reduce the amount of gathered and stored monitoring data, e.g., by a factor of  56 in comparison to the Ganglia distributed monitoring system. A simple scaling study reveals, however, that further efforts are needed in reducing the amount of data to monitor future-generation extreme-scale systems with up to 1,000,000 nodes. The implemented solution did not had a measurable performance impact as the 32-node test system did not produce enough monitoring data to interfere with running applications.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/boehm10aggregation.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/boehm10aggregation.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#boehm10aggregation\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Antonina Litvinova, Christian Engelmann, and Stephen L. Scott. <b>A Proactive Fault Tolerance Framework for High-Performance Computing<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.iasted.org\/conferences\/home-676.html\" target=\"www.iasted.org\/conferences\/home-676.html\">9th IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN) 2010<\/a><\/i>, Innsbruck, Austria, February 16-18, 2010. <a href=\"http:\/\/www.actapress.com\" target=\"www.actapress.com\">ACTA Press, Calgary, AB, Canada<\/a>. ISBN 978-0-88986-783-3. DOI <a href=\"http:\/\/dx.doi.org\/10.2316\/P.2010.676-024\" target=\"publication\">10.2316\/P.2010.676-024<\/a>. <a href=\"javascript:showAbstract('As high-performance computing (HPC) systems continue to increase in scale, their mean-time to interrupt decreases respectively. The current state of practice for fault tolerance (FT) is checkpoint\/restart. However, with increasing error rates, increasing aggregate memory and not proportionally increasing I\/O capabilities, it is becoming less efficient. Proactive FT avoids experiencing failures through preventative measures, such as by migrating application parts away from nodes that are about to fail. This paper presents a proactive FT framework that performs environmental monitoring, event logging, parallel job monitoring and resource monitoring to analyze HPC system reliability and to perform FT through such preventative actions.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/litvinova10proactive.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/litvinova10proactive.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#litvinova10proactive\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Narate Taerat, Nichamon Naksinehaboon, Clayton Chandler, James Elliott, Chokchai (Box) Leangsuksun, George Ostrouchov, Stephen L. Scott, and Christian Engelmann. <b>Blue Gene\/L Log Analysis and Time to Interrupt Estimation<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.ares-conference.eu\/ares2009\" target=\"www.ares-conference.eu\/ares2009\">4th International Conference on Availability, Reliability and Security (ARES) 2009<\/a><\/i>, pages 173-180, Fukuoka, Japan, March 16-19, 2009. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-1-4244-3572-2. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/ARES.2009.105\" target=\"publication\">10.1109\/ARES.2009.105<\/a>. Acceptance rate 25.0% (40\/160). <a href=\"javascript:showAbstract('System- and application-level failures could be characterized by analyzing relevant log files. The resulting data might then be used in numerous studies on and future developments for the mission-critical and large scale computational architecture, including fields such as failure prediction, reliability modeling, performance modeling and power awareness. In this paper, system logs covering a six month period of the Blue Gene\/L supercomputer were obtained and subsequently analyzed. Temporal filtering was applied to remove duplicated log messages. Optimistic and pessimistic perspectives were exerted on filtered log information to observe failure behavior within the system. Further, various time to repair factors were applied to obtain application time to interrupt, which will be exploited in further resilience modeling research.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/taerat09blue.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"?page_id=55#taerat09blue\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann, Hong H. Ong, and Stephen L. Scott. <b>Evaluating the Shared Root File System Approach for Diskless High-Performance Computing Systems<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.linuxclustersinstitute.org\/conferences\" target=\"www.linuxclustersinstitute.org\/conferences\">10th LCI International Conference on High-Performance Clustered Computing (LCI) 2009<\/a><\/i>, Boulder, CO, USA, March 9-12, 2009. <a href=\"javascript:showAbstract('Diskless high-performance computing (HPC) systems utilizing networked storage have become popular in the last several years. Removing disk drives significantly increases compute node reliability as they are known to be a major source of failures. Furthermore, networked storage solutions utilizing parallel I\/O and replication are able to provide increased scalability and availability. Reducing a compute node to processor(s), memory and network interface(s) greatly reduces its physical size, which in turn allows for large-scale dense HPC solutions. However, one major obstacle is the requirement by certain operating systems (OSs), such as Linux, for a root file system. While one solution is to remove this requirement from the OS, another is to share the root file system over the networked storage. This paper evaluates three networked file system solutions, NFSv4, Lustre and PVFS2, with respect to their performance, scalability, and availability features for servicing a common root file system in a diskless HPC configuration. Our findings indicate that Lustre is a viable solution as it meets both, scaling and performance requirements. However, certain availability issues regarding single points of failure and control need to be considered.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann09evaluating.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/engelmann09evaluating.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann09evaluating\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann, Geoffroy R. Vall&eacute;e, Thomas Naughton, and Stephen L. Scott. <b>Proactive Fault Tolerance Using Preemptive Migration<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.pdp2009.org\" target=\"www.pdp2009.org\">17th Euromicro International Conference on Parallel, Distributed, and network-based Processing (PDP) 2009<\/a><\/i>, pages 252-257, Weimar, Germany, February 18-20, 2009. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-0-7695-3544-9. ISSN 1066-6192. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/PDP.2009.31\" target=\"publication\">10.1109\/PDP.2009.31<\/a>. Acceptance rate 42.0% (58\/138). <a href=\"javascript:showAbstract('Proactive fault tolerance (FT) in high-performance computing is a concept that prevents compute node failures from impacting running parallel applications by preemptively migrating application parts away from nodes that are about to fail. This paper provides a foundation for proactive FT by defining its architecture and classifying implementation options. This paper further relates prior work to the presented architecture and classification, and discusses the challenges ahead for needed supporting technologies.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann09proactive.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/engelmann09proactive.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann09proactive\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Alessandro Valentini, Christian Di Biagio, Fabrizio Batino, Guido Pennella, Fabrizio Palma, and Christian Engelmann. <b>High Performance Computing with Harness over InfiniBand<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.pdp2009.org\" target=\"www.pdp2009.org\">17th Euromicro International Conference on Parallel, Distributed, and network-based Processing (PDP) 2009<\/a><\/i>, pages 151-154, Weimar, Germany, February 18-20, 2009. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-0-7695-3544-9. ISSN 1066-6192. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/PDP.2009.64\" target=\"publication\">10.1109\/PDP.2009.64<\/a>. Acceptance rate 42.0% (58\/138). <a href=\"javascript:showAbstract('Harness is an adaptable and plug-in-based middleware framework able to support distributed parallel computing. By now, it is based on the Ethernet protocol which cannot guarantee high performance throughput and Real Time (determinism) performance. During last years, both the research and industry environments have developed both new network architectures (InfiniBand, Myrinet, iWARP, etc.) to avoid those limits. This paper concerns the integration between Harness and InfiniBand focusing on two solutions: IP over InfiniBand (IPoIB) and Socket Direct Protocol (SDP) technology. Those allow Harness middleware to take advantage of the enhanced features provided by InfiniBand.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/valentini09high.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"?page_id=55#valentini09high\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann, Hong H. Ong, and Stephen L. Scott. <b>The Case for Modular Redundancy in Large-Scale High Performance Computing Systems<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.iasted.org\/conferences\/home-641.html\" target=\"www.iasted.org\/conferences\/home-641.html\">8th IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN) 2009<\/a><\/i>, pages 189-194, Innsbruck, Austria, February 16-18, 2009. <a href=\"http:\/\/www.actapress.com\" target=\"www.actapress.com\">ACTA Press, Calgary, AB, Canada<\/a>. ISBN 978-0-88986-784-0. <a href=\"javascript:showAbstract('Recent investigations into resilience of large-scale high-performance computing (HPC) systems showed a continuous trend of decreasing reliability and availability. Newly installed systems have a lower mean-time to failure (MTTF) and a higher mean-time to recover (MTTR) than their predecessors. Modular redundancy is being used in many mission critical systems today to provide for resilience, such as for aerospace and command &amp; control systems. The primary argument against modular redundancy for resilience in HPC has always been that the capability of a HPC system, and respective return on investment, would be significantly reduced. We argue that modular redundancy can significantly increase compute node availability as it removes the impact of scale from single compute node MTTR. We further argue that single compute nodes can be much less reliable, and therefore less expensive, and still be highly available, if their MTTR\/MTTF ratio is maintained.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann09case.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/engelmann09case.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann09case\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Chao Wang, Frank Mueller, Christian Engelmann, and Stephen L. Scott. <b>Proactive Process-Level Live Migration in HPC Environments<\/b>. In <i>Proceedings of the <a href=\"http:\/\/sc08.supercomputing.org\" target=\"sc08.supercomputing.org\">21st IEEE\/ACM International Conference on High Performance Computing, Networking, Storage and Analysis (SC) 2008<\/a><\/i>, pages 1-12, Austin, TX, USA, November 15-21, 2008. <a href=\"http:\/\/www.acm.org\" target=\"www.acm.org\">ACM Press, New York, NY, USA<\/a>. ISBN 978-1-4244-2835-9. DOI <a href=\"http:\/\/dx.doi.org\/10.1145\/1413370.1413414\" target=\"publication\">10.1145\/1413370.1413414<\/a>. Acceptance rate 21.3% (59\/277). <a href=\"javascript:showAbstract('As the number of nodes in high-performance computing environments keeps increasing, faults are becoming common place. Reactive fault tolerance (FT) often does not scale due to massive I\/O requirements and relies on manual job resubmission. This work complements reactive with proactive FT at the process level. Through health monitoring, a subset of node failures can be anticipated when one&amp;#39;s health deteriorates. A novel process-level live migration mechanism supports continued execution of applications during much of processes migration. This scheme is integrated into an MPI execution environment to transparently sustain health-inflicted node failures, which eradicates the need to restart and requeue MPI jobs. Experiments indicate that 1-6.5 seconds of prior warning are required to successfully trigger live process migration while similar operating system virtualization mechanisms require 13-24 seconds. This self-healing approach complements reactive FT by nearly cutting the number of checkpoints in half when 70% of the faults are handled proactively.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/wang08proactive.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/wang08proactive.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#wang08proactive\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann, Stephen L. Scott, Chokchai (Box) Leangsuksun, and Xubin (Ben) He. <b>Symmetric Active\/Active Replication for Dependent Services<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.ares-conference.eu\/ares2008\" target=\"www.ares-conference.eu\/ares2008\">3rd International Conference on Availability, Reliability and Security (ARES) 2008<\/a><\/i>, pages 260-267, Barcelona, Spain, March 4-7, 2008. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-0-7695-3102-1. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/ARES.2008.64\" target=\"publication\">10.1109\/ARES.2008.64<\/a>. Acceptance rate 21.1% (40\/190). <a href=\"javascript:showAbstract('During the last several years, we have established the symmetric active\/active replication model for service-level high availability and implemented several proof-of-concept prototypes. One major deficiency of our model is its inability to deal with dependent services, since its original architecture is based on the client-service model. This paper extends our model to dependent services using its already existing mechanisms and features. The presented concept is based on the idea that a service may also be a client of another service, and multiple services may be clients of each other. A high-level abstraction is used to illustrate dependencies between clients and services, and to decompose dependencies between services into respective client-service dependencies. This abstraction may be used for providing high availability in distributed computing systems with complex service-oriented architectures.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann08symmetric.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/engelmann08symmetric.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann08symmetric\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Geoffroy R. Vall&eacute;e, Kulathep Charoenpornwattana, Christian Engelmann, Anand Tikotekar, Chokchai (Box) Leangsuksun, Thomas Naughton, and Stephen L. Scott. <b>A Framework For Proactive Fault Tolerance<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.ares-conference.eu\/ares2008\" target=\"www.ares-conference.eu\/ares2008\">3rd International Conference on Availability, Reliability and Security (ARES) 2008<\/a><\/i>, pages 659-664, Barcelona, Spain, March 4-7, 2008. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-0-7695-3102-1. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/ARES.2008.171\" target=\"publication\">10.1109\/ARES.2008.171<\/a>. Acceptance rate 21.1% (40\/190). <a href=\"javascript:showAbstract('Fault tolerance is a major concern to guarantee availability of critical services as well as application execution. Traditional approaches for fault tolerance include checkpoint\/restart or duplication. However it is also possible to anticipate failures and proactively take action before failures occur in order to minimize failure impact on the system and application execution. This document presents a proactive fault tolerance framework. This framework can use different proactive fault tolerance mechanisms, i.e. migration and pause\/unpause. The framework also allows the implementation of new proactive fault tolerance policies thanks to a modular architecture. A first proactive fault tolerance policy has been implemented and preliminary experimentations have been done based on system-level virtualization and compared with results obtained by simulation.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/vallee08framework.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/vallee08framework.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#vallee08framework\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Bj&ouml;rn K&ouml;nning, Christian Engelmann, Stephen L. Scott, and George A. (Al) Geist. <b>Virtualized Environments for the Harness High Performance Computing Workbench<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.pdp2008.org\" target=\"www.pdp2008.org\">16th Euromicro International Conference on Parallel, Distributed, and network-based Processing (PDP) 2008<\/a><\/i>, pages 133-140, Toulouse, France, February 13-15, 2008. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-0-7695-3089-5. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/PDP.2008.14\" target=\"publication\">10.1109\/PDP.2008.14<\/a>. Acceptance rate 40% (83\/207). <a href=\"javascript:showAbstract('This paper describes recent accomplishments in providing a virtualized environment concept and prototype for scientific application development and deployment as part of the Harness High Performance Computing (HPC) Workbench research effort. The presented work focuses on tools and mechanisms that simplify scientific application development and deployment tasks, such that only minimal adaptation is needed when moving from one HPC system to another or after HPC system upgrades. The overall technical approach focuses on the concept of adapting the HPC system environment to the actual needs of individual scientific applications instead of the traditional scheme of adapting scientific applications to individual HPC system environment properties. The presented prototype implementation is based on the mature and lightweight chroot virtualization approach for Unix-type systems with a focus on virtualized file system structure and virtualized shell environment variables utilizing virtualized environment configuration descriptions in Extensible Markup Language (XML) format. The presented work can be easily extended to other virtualization technologies, such as system-level virtualization solutions using hypervisors.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/koenning08virtualized.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/koenning08virtualized.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#koenning08virtualized\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Geoffroy R. Vall&eacute;e, Thomas Naughton, Christian Engelmann, Hong H. Ong, and Stephen L. Scott. <b>System-level Virtualization for High Performance Computing<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.pdp2008.org\" target=\"www.pdp2008.org\">16th Euromicro International Conference on Parallel, Distributed, and network-based Processing (PDP) 2008<\/a><\/i>, pages 636-643, Toulouse, France, February 13-15, 2008. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-0-7695-3089-5. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/PDP.2008.85\" target=\"publication\">10.1109\/PDP.2008.85<\/a>. Acceptance rate 40% (83\/207). <a href=\"javascript:showAbstract('System-level virtualization has been a research topic since the 70`s but regained popularity during the past few years because of the availability of efficient solution such as Xen and the implementation of hardware support in commodity processors (e.g. Intel-VT, AMD-V). However, a majority of system-level virtualization projects is guided by the server consolidation market. As a result, current virtualization solutions appear to not be suitable for high performance computing (HPC) which is typically based on large-scale systems. On another hand there is significant interest in exploiting virtual machines (VMs) within HPC for a number of other reasons. By virtualizing the machine, one is able to run a variety of operating systems and environments as needed by the applications. Virtualization allows users to isolate workloads, improving security and reliability. It is also possible to support non-native environments and\/or legacy operating environments through virtualization. In addition, it is possible to balance work loads, use migration techniques to relocate applications from failing machines, and isolate fault systems for repair. This document presents the challenges for the implementation of a system-level virtualization solution for HPC. It also presents a brief survey of the different approaches and techniques to address these challenges.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/vallee08system.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/vallee08system.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#vallee08system\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Li Ou, Christian Engelmann, Xubin (Ben) He, Xin Chen, and Stephen L. Scott. <b>Symmetric Active\/Active Metadata Service for Highly Available Cluster Storage Systems<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.iasted.org\/conferences\/home-590.html\" target=\"www.iasted.org\/conferences\/home-590.html\">19th IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS) 2007<\/a><\/i>, Cambridge, MA, USA, November 19-21, 2007. <a href=\"http:\/\/www.actapress.com\" target=\"www.actapress.com\">ACTA Press, Calgary, AB, Canada<\/a>. ISBN 978-0-88986-703-1. Acceptance rate 49%. <a href=\"javascript:showAbstract('In a typical distributed storage system, metadata is stored and managed by dedicated metadata servers. One way to improve the availability of distributed storage systems is to deploy multiple metadata servers. Past research focused on the active\/standby model, where each active server has at least one redundant idle backup. However, interruption of service and loss of service state may occur during a fail-over depending on the used replication technique. The research in this paper targets the symmetric active\/active replication model using multiple redundant service nodes running in virtual synchrony. In this model, service node failures do not cause a fail-over to a backup and there is no disruption of service or loss of service state. We propose a fast delivery protocol to reduce the latency of total order broadcast. Our prototype implementation shows that high availability of metadata servers can be achieved with an acceptable performance trade-off using the active\/active metadata server solution.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/ou07symmetric.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/ou07symmetric.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#ou07symmetric\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Emanuele Di Saverio, Marco Cesati, Christian Di Biagio, Guido Pennella, and Christian Engelmann. <b>Distributed Real-Time Computing with Harness<\/b>. In <i>Lecture Notes in Computer Science: Proceedings of the <a href=\"http:\/\/pvmmpi07.lri.fr\" target=\"pvmmpi07.lri.fr\">14th European PVM\/MPI Users` Group Meeting (EuroPVM\/MPI) 2007<\/a><\/i>, pages 281-288, Paris, France, September 30 &#8211; October 3, 2007. <a href=\"http:\/\/www.springer.com\" target=\"www.springer.com\">Springer Verlag, Berlin, Germany<\/a>. ISBN 978-3-540-75415-2. ISSN 0302-9743. DOI <a href=\"http:\/\/dx.doi.org\/10.1007\/978-3-540-75416-9_39\" target=\"publication\">10.1007\/978-3-540-75416-9_39<\/a>. <a href=\"javascript:showAbstract('Modern parallel and distributed computing solutions are often built onto a middleware software layer providing a higher and common level of service between computational nodes. Harness is an adaptable, plugin-based middleware framework for parallel and distributed computing. This paper reports recent research and development results of using Harness for real-time distributed computing applications in the context of an industrial environment with the needs to perform several safety critical tasks. The presented work exploits the modular architecture of Harness in conjunction with a lightweight threaded implementation to resolve several real-time issues by adding three new Harness plug-ins to provide a prioritized lightweight execution environment, low latency communication facilities, and local timestamped event logging.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/disaverio07distributed.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/disaverio07distributed.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#disaverio07distributed\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Li Ou, Xubin (Ben) He, Christian Engelmann, and Stephen L. Scott. <b>A Fast Delivery Protocol for Total Order Broadcasting<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.icccn.org\/icccn07\" target=\"www.icccn.org\/icccn07\">16th IEEE International Conference on Computer Communications and Networks (ICCCN) 2007<\/a><\/i>, pages 730-734, Honolulu, HI, USA, August 13-16, 2007. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-1-42441-251-8. ISSN 1095-2055. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/ICCCN.2007.4317904\" target=\"publication\">10.1109\/ICCCN.2007.4317904<\/a>. Acceptance rate 29.1% (160\/550). <a href=\"javascript:showAbstract('Sequencer, privilege-based, and communication history algorithms are popular approaches to implement total ordering, where communication history algorithms are most suitable for parallel computing systems, because they provide best performance under heavy work load. Unfortunately, post-transmission delay of communication history algorithms is most apparent when a system is idle. In this paper, we propose a fast delivery protocol to reduce the latency of message ordering. The protocol optimizes the total ordering process by waiting for messages only from a subset of the machines in the group, and by fast acknowledging messages on behalf of other machines. Our test results indicate that the fast delivery protocol is suitable for both idle and heavy load systems, while reducing the latency of message ordering.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/ou07fast.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/ou07fast.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#ou07fast\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Arun B. Nagarajan, Frank Mueller, Christian Engelmann, and Stephen L. Scott. <b>Proactive Fault Tolerance for HPC with Xen Virtualization<\/b>. In <i>Proceedings of the <a href=\"http:\/\/ics07.ac.upc.edu\" target=\"ics07.ac.upc.edu\">21st ACM International Conference on Supercomputing (ICS) 2007<\/a><\/i>, pages 23-32, Seattle, WA, USA, June 16-20, 2007. <a href=\"http:\/\/www.acm.org\" target=\"www.acm.org\">ACM Press, New York, NY, USA<\/a>. ISBN 978-1-59593-768-1. DOI <a href=\"http:\/\/dx.doi.org\/10.1145\/1274971.1274978\" target=\"publication\">10.1145\/1274971.1274978<\/a>. Acceptance rate 23.6% (29\/123). <a href=\"javascript:showAbstract('Large-scale parallel computing is relying increasingly on clusters with thousands of processors. At such large counts of compute nodes, faults are becoming common place. Current techniques to tolerate faults focus on reactive schemes to recover from faults and generally rely on a checkpoint\/restart mechanism. Yet, in today`s systems, node failures can often be anticipated by detecting a deteriorating health status. Instead of a reactive scheme for fault tolerance (FT), we are promoting a proactive one where processes automatically migrate from unhealthy nodes to healthy ones. Our approach relies on operating system virtualization techniques exemplified by but not limited to Xen. This paper contributes an automatic and transparent mechanism for proactive FT for arbitrary MPI applications. It leverages virtualization techniques combined with health monitoring and load-based migration. We exploit Xen`s live migration mechanism for a guest operating system (OS) to migrate an MPI task from a health-deteriorating node to a healthy one without stopping the MPI task during most of the migration. Our proactive FT daemon orchestrates the tasks of health monitoring, load determination and initiation of guest OS migration. Experimental results demonstrate that live migration hides migration costs and limits the overhead to only a few seconds making it an attractive approach to realize FT in HPC systems. Overall, our enhancements make proactive FT a valuable asset for long-running MPI application that is complementary to reactive FT using full checkpoint\/restart schemes since checkpoint frequencies can be reduced as fewer unanticipated failures are encountered. In the context of OS virtualization, we believe that this is the first comprehensive study of proactive fault tolerance where live migration is actually triggered by health monitoring.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/nagarajan07proactive.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/nagarajan07proactive.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#nagarajan07proactive\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann, Stephen L. Scott, Chokchai (Box) Leangsuksun, and Xubin (Ben) He. <b>On Programming Models for Service-Level High Availability<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.ares-conference.eu\/ares2007\" target=\"www.ares-conference.eu\/ares2007\">2nd International Conference on Availability, Reliability and Security (ARES) 2007<\/a><\/i>, pages 999-1006, Vienna, Austria, April 10-13, 2007. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 0-7695-2775-2. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/ARES.2007.109\" target=\"publication\">10.1109\/ARES.2007.109<\/a>. Acceptance rate 28.3% (60\/212). <a href=\"javascript:showAbstract('This paper provides an overview of existing programming models for service-level high availability and investigates their differences, similarities, advantages, and disadvantages. Its goal is to help to improve reuse of code and to allow adaptation to quality of service requirements by using a uniform programming model description. It further aims at encouraging a discussion about these programming models and their provided quality of service, such as availability, performance, serviceability, usability, and applicability. Within this context, the presented research focuses on providing high availability for services running on head and service nodes of high-performance computing systems.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann07programming.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/engelmann07programming.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann07programming\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Chao Wang, Frank Mueller, Christian Engelmann, and Stephen L. Scott. <b>A Job Pause Service under LAM\/MPI+BLCR for Transparent Fault Tolerance<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.ipdps.org\/ipdps2007\" target=\"www.ipdps.org\/ipdps2007\">21st IEEE International Parallel and Distributed Processing Symposium (IPDPS) 2007<\/a><\/i>, pages 1-10, Long Beach, CA, USA, March 26-30, 2007. <a href=\"http:\/\/www.acm.org\" target=\"www.acm.org\">ACM Press, New York, NY, USA<\/a>. ISBN 978-1-59593-768-1. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/IPDPS.2007.370307\" target=\"publication\">10.1109\/IPDPS.2007.370307<\/a>. Acceptance rate 26% (109\/419). <a href=\"javascript:showAbstract('Checkpoint\/restart (C\/R) has become a requirement for long-running jobs in large-scale clusters due to a mean-time-to-failure (MTTF) in the order of hours. After a failure, C\/R mechanisms generally require a complete restart of an MPI job from the last checkpoint. A complete restart, however, is unnecessary since all but one node are typically still alive. Furthermore, a restart may result in lengthy job requeuing even though the original job had not exceeded its time quantum. In this paper, we overcome these shortcomings. Instead of job restart, we have developed a transparent mechanism for job pause within LAM\/MPI+BLCR. This mechanism allows live nodes to remain active and roll back to the last checkpoint while failed nodes are dynamically replaced by spares before resuming from the last checkpoint. Our methodology includes LAM\/MPI enhancements in support of scalable group communication with fluctuating number of nodes, reuse of network connections, transparent coordinated checkpoint scheduling and a BLCR enhancement for job pause. Experiments in a cluster with the NAS Parallel Benchmark suite show that our overhead for job pause is comparable to that of a complete job restart. A minimal overhead of 5.6% is only incurred in case migration takes place while the regular checkpoint overhead remains unchanged. Yet, our approach alleviates the need to reboot the LAM run-time environment, which accounts for considerable overhead resulting in net savings of our scheme in the experiments. Our solution further provides full transparency and automation with the additional benefit of reusing existing resources. Executing continues after failures within the scheduled job, \\em \\textiti.e., the application staging overhead is not incurred again in contrast to a restart. Our scheme offers additional potential for savings through incremental checkpointing and proactive diskless live migration, which we are currently working on.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/wang07job.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/wang07job.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#wang07job\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Kai Uhlemann, Christian Engelmann, and Stephen L. Scott. <b>JOSHUA: Symmetric Active\/Active Replication for Highly Available HPC Job and Resource Management<\/b>. In <i>Proceedings of the <a href=\"http:\/\/cluster2006.org\" target=\"cluster2006.org\">8th IEEE International Conference on Cluster Computing (Cluster) 2006<\/a><\/i>, pages 1-10, Barcelona, Spain, September 25-28, 2006. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 1-4244-0328-6. ISSN 1552-5244. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/CLUSTR.2006.311855\" target=\"publication\">10.1109\/CLUSTR.2006.311855<\/a>. Acceptance rate 33.1% (42\/127). <a href=\"javascript:showAbstract('Most of today`s HPC systems employ a single head node for control, which represents a single point of failure as it interrupts an entire HPC system upon failure. Furthermore, it is also a single point of control as it disables an entire HPC system until repair. One of the most important HPC system service running on the head node is the job and resource management. If it goes down, all currently running jobs loose the service they report back to. They have to be restarted once the head node is up and running again. With this paper, we present a generic approach for providing symmetric active\/active replication for highly available HPC job and resource management. The JOSHUA solution provides a virtually synchronous environment for continuous availability without any interruption of service and without any loss of state. Replication is performed externally via the PBS service interface without the need to modify any service code. Test results as well as availability analysis of our proof-of-concept prototype implementation show that continuous availability can be provided by JOSHUA with an acceptable performance trade-off.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/uhlemann06joshua.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/uhlemann06joshua.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#uhlemann06joshua\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Ronald Baumann, Christian Engelmann, and George A. (Al) Geist. <b>A Parallel Plug-in Programming Paradigm<\/b>. In <i>Lecture Notes in Computer Science: Proceedings of the <a href=\"http:\/\/hpcc06.lrr.in.tum.de\" target=\"hpcc06.lrr.in.tum.de\">7th International Conference on High Performance Computing and Communications (HPCC) 2006<\/a><\/i>, pages 823-832, Munich, Germany, September 13-15, 2006. <a href=\"http:\/\/www.springer.com\" target=\"www.springer.com\">Springer Verlag, Berlin, Germany<\/a>. ISBN 978-3-540-39368-9. ISSN 0302-9743. DOI <a href=\"http:\/\/dx.doi.org\/10.1007\/11847366_85\" target=\"publication\">10.1007\/11847366_85<\/a>. <a href=\"javascript:showAbstract('Software component architectures allow assembly of applications from individual software modules based on clearly defined programming interfaces, thus improving the reuse of existing solutions and simplifying application development. Furthermore, the plug-in programming paradigm additionally enables runtime reconfigurability, making it possible to adapt to changing application needs, such as different application phases, and system properties, like resource availability, by loading\/unloading appropriate software modules. Similar to parallel programs, parallel plug-ins are an abstraction for a set of cooperating individual plug-ins within a parallel application utilizing a software component architecture. Parallel programming paradigms apply to parallel plug-ins in the same way they apply to parallel programs. The research presented in this paper targets the clear definition of parallel plug-ins and the development of a parallel plug-in programming paradigm.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/baumann06parallel.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/baumann06parallel.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#baumann06parallel\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Jyothish Varma, Chao Wang, Frank Mueller, Christian Engelmann, and Stephen L. Scott. <b>Scalable, Fault-Tolerant Membership for MPI Tasks on HPC Systems<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.ics-conference.org\/2006\" target=\"www.ics-conference.org\/2006\">20th ACM International Conference on Supercomputing (ICS) 2006<\/a><\/i>, pages 219-228, Cairns, Australia, June 28-30, 2006. <a href=\"http:\/\/www.acm.org\" target=\"www.acm.org\">ACM Press, New York, NY, USA<\/a>. ISBN 1-59593-282-8. DOI <a href=\"http:\/\/dx.doi.org\/10.1145\/1183401.1183433\" target=\"publication\">10.1145\/1183401.1183433<\/a>. Acceptance rate 26.2% (37\/141). <a href=\"javascript:showAbstract('Reliability is increasingly becoming a challenge for high-performance computing (HPC) systems with thousands of nodes, such as IBM`s Blue Gene\/L. A shorter mean-time-to-failure can be addressed by adding fault tolerance to reconfigure working nodes to ensure that communication and computation can progress. However, existing approaches fall short in providing scalability and small reconfiguration overhead within the fault-tolerant layer. This paper contributes a scalable approach to reconfigure the communication infrastructure after node failures. We propose a decentralized (peer-to-peer) protocol that maintains a consistent view of active nodes in the presence of faults. Our protocol shows response times in the order of hundreds of microseconds and single-digit milliseconds for  reconfiguration using MPI over Blue Gene\/L and TCP over  Gigabit, respectively. The protocol can be adapted to match the network topology to further increase performance. We also verify experimental results against a performance model, which demonstrates the scalability of the approach. Hence, the membership service is suitable for deployment in the communication layer of MPI runtime systems, and we have integrated an early version into LAM\/MPI.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/varma06scalable.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/varma06scalable.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#varma06scalable\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Daniel I. Okunbor, Christian Engelmann, and Stephen L. Scott. <b>Exploring Process Groups for Reliability, Availability and Serviceability of Terascale Computing Systems<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.atiner.gr\/docs\/2006AAAPROGRAM_COMP.htm\" target=\"www.atiner.gr\/docs\/2006AAAPROGRAM_COMP.htm\">2nd International Conference on Computer Science and Information Systems 2006<\/a><\/i>, Athens, Greece, June 19-21, 2006. <a href=\"javascript:showAbstract('This paper presents various aspects of reliability, availability and serviceability (RAS) systems as they relate to group communication service, including reliable and total order multicast\/broadcast, virtual synchrony, and failure detection. While the issue of availability, particularly high availability using replication-based architectures has recently received upsurge research interests, much still have to be done in understanding the basic underlying concepts for achieving RAS systems, especially in high-end and high performance computing (HPC) communities. Various attributes of group communication service and the prototype of symmetric active replication following ideas utilized in the Newtop protocol will be discussed. We explore the application of group communication service for RAS HPC, laying the groundwork for its integrated model.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/okunbor06exploring.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"?page_id=55#okunbor06exploring\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Kshitij Limaye, Chokchai (Box) Leangsuksun, Zeno Greenwood, Stephen L. Scott, Christian Engelmann, Richard M. Libby, and Kasidit Chanchio. <b>Job-Site Level Fault Tolerance for Cluster and Grid Environments<\/b>. In <i>Proceedings of the <a href=\"http:\/\/cluster2005.org\" target=\"cluster2005.org\">7th IEEE International Conference on Cluster Computing (Cluster) 2005<\/a><\/i>, pages 1-9, Boston, MA, USA, September 26-30, 2005. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 0-7803-9486-0. ISSN 1552-5244. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/CLUSTR.2005.347043\" target=\"publication\">10.1109\/CLUSTR.2005.347043<\/a>. Acceptance rate 39.6% (45\/138). <a href=\"javascript:showAbstract('In order to adopt high performance clusters and Grid computing for mission critical applications, fault tolerance is a necessity. Common fault tolerance techniques in distributed systems are normally achieved with checkpoint-recovery and job replication on alternative resources, in cases of a system outage. The first approach depends on the system`s MTTR while the latter approach depends on the availability of alternative sites to run replicas. There is a need for complementing these approaches by proactively handling failures at a job-site level, ensuring the system high availability with no loss of user submitted jobs. This paper discusses a novel fault tolerance technique  that enables the job-site recovery in Beowulf cluster-based grid environments, whereas existing techniques give up a failed system by seeking alternative resources. Our results suggest sizable aggregate performance improvement during an implementation of our method in Globus-enabled HA-OSCAR. The technique called Smart Failover provides a transparent and graceful recovery mechanism that saves job states in a local job-manager queue and transfers those states to the backup server periodically, and in critical system events. Thus whenever a failover occurs, the backup server is able to restart the jobs from their last saved state.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/limaye05jobsite.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"?page_id=55#limaye05jobsite\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Hertong Song, Chokchai (Box) Leangsuksun, Raja Nassar, Yudan Liu, Christian Engelmann, and Stephen L. Scott. <b>UML-based Beowulf Cluster Availability Modeling<\/b>. In <i><a href=\"http:\/\/www.world-academy-of-science.org\/IMCSE2005\/ws\/SERP\" target=\"www.world-academy-of-science.org\/IMCSE2005\/ws\/SERP\">International Conference on Software Engineering Research and Practice (SERP) 2005<\/a><\/i>, pages 161-167, Las Vegas, NV, USA, June 27-30, 2005. CSREA Press. ISBN 1-932415-49-1. <a href=\"?page_id=55#song05umlbased\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann and George A. (Al) Geist. <b>Super-Scalable Algorithms for Computing on 100,000 Processors<\/b>. In <i>Lecture Notes in Computer Science: Proceedings of the <a href=\"http:\/\/www.iccs-meeting.org\/iccs2005\" target=\"www.iccs-meeting.org\/iccs2005\">5th International Conference on Computational Science (ICCS) 2005<\/a>, Part I<\/i>, pages 313-320, Atlanta, GA, USA, May 22-25, 2005. <a href=\"http:\/\/www.springer.com\" target=\"www.springer.com\">Springer Verlag, Berlin, Germany<\/a>. ISBN 978-3-540-26032-5. ISSN 0302-9743. DOI <a href=\"http:\/\/dx.doi.org\/10.1007\/11428831_39\" target=\"publication\">10.1007\/11428831_39<\/a>. Acceptance rate 35%. <a href=\"javascript:showAbstract('In the next five years, the number of processors in high-end systems for scientific computing is expected to rise to tens and even hundreds of thousands. For example, the IBM Blue Gene\/L can have up to 128,000 processors and the delivery of the first system is scheduled for 2005. Existing deficiencies in scalability and fault-tolerance of scientific applications need to be addressed soon. If the number of processors grows by a magnitude and efficiency drops by a magnitude, the overall effective computing performance stays the same. Furthermore, the mean time to interrupt of high-end computer systems decreases with scale and complexity. In a 100,000-processor system, failures may occur every couple of minutes and traditional checkpointing may no longer be feasible. With this paper, we summarize our recent research in super-scalable algorithms for computing on 100,000 processors. We introduce the algorithm properties of scale invariance and natural fault tolerance, and discuss how they can be applied to two different classes of algorithms. We also describe a super-scalable diskless checkpointing algorithm for problems that can`t be transformed into a super-scalable variant, or where other solutions are more efficient. Finally, a 100,000-processor simulator is presented as a platform for testing and experimentation.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann05superscalable.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/engelmann05superscalable.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann05superscalable\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<\/ol>\n<p><em><small>Symbols: <img decoding=\"async\" style=\"border-style: none;\" src=\"images\/txt.gif\" border=\"0\" alt=\"Abstract\" height=\"10pt\"> Abstract, <img decoding=\"async\" style=\"border-style: none;\" src=\"images\/pdf.gif\" border=\"0\" alt=\"Publication\" height=\"10pt\"> Publication, <img decoding=\"async\" style=\"border-style: none;\" src=\"images\/ppt.gif\" border=\"0\" alt=\"Presentation\" height=\"10pt\"> Presentation, <img decoding=\"async\" style=\"border-style: none;\" src=\"images\/bib.gif\" border=\"0\" alt=\"BibTeX Citation\" height=\"10pt\"> BibTeX Citation<\/small><\/em><\/p>\n<p><script language=\"JavaScript\">\nfunction showAbstract (text) {\n  var width  = 400;\n  var height = 400;\n  var left   = (screen.width  - width ) \/ 2;\n  var top    = (screen.height - height) \/ 2;\n  var win    = window.open('',\n                           'Abstract',\n                           'width='  + width  + ', ' + \n                           'height=' + height + ', ' +\n                           'left='   + left   + ', ' +\n                           'top='    + top    + ', ' +\n                           'toolbar=no, '     +\n                           'location=no, '    +\n                           'directories=no, ' +\n                           'status=no, '      +\n                           'menubar=no, '     +\n                           'copyhistory=no, ' +\n                           'scrollbars=yes, ' +\n                           'resizable=yes')\n  win.document.write(text);\n  win.document.close();\n}\n<\/script><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Pedro Valero-Lara, Aaron Young, Thomas Naughton, Christian Engelmann, Al Geist, Jeffrey S. Vetter, Keita Teranishi, and William F. Godoy. ChatMPI: LLM-Driven MPI Code Generation for HPC Workloads. In Proceedings of the Supercomputing Asia \/ International Conference on High Performance Computing in the Asia-Pacific Region (SCA\/HPCAsia) 2026, pages 19-30, Osaka, Japan, January 26-29, 2026. ACM Press,&hellip;&nbsp;<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":16,"menu_order":1,"comment_status":"closed","ping_status":"closed","template":"","meta":{"neve_meta_sidebar":"","neve_meta_container":"","neve_meta_enable_content_width":"off","neve_meta_content_width":100,"neve_meta_title_alignment":"","neve_meta_author_avatar":"","neve_post_elements_order":"","neve_meta_disable_header":"","neve_meta_disable_footer":"","neve_meta_disable_title":"","footnotes":""},"class_list":["post-20","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.christian-engelmann.info\/index.php?rest_route=\/wp\/v2\/pages\/20","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.christian-engelmann.info\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.christian-engelmann.info\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.christian-engelmann.info\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.christian-engelmann.info\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=20"}],"version-history":[{"count":25,"href":"https:\/\/www.christian-engelmann.info\/index.php?rest_route=\/wp\/v2\/pages\/20\/revisions"}],"predecessor-version":[{"id":1391,"href":"https:\/\/www.christian-engelmann.info\/index.php?rest_route=\/wp\/v2\/pages\/20\/revisions\/1391"}],"up":[{"embeddable":true,"href":"https:\/\/www.christian-engelmann.info\/index.php?rest_route=\/wp\/v2\/pages\/16"}],"wp:attachment":[{"href":"https:\/\/www.christian-engelmann.info\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=20"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}