{"id":433,"date":"2023-11-21T08:00:40","date_gmt":"2023-11-21T08:00:40","guid":{"rendered":"https:\/\/christian-engelmann.de\/?page_id=433"},"modified":"2024-11-21T21:39:31","modified_gmt":"2024-11-21T21:39:31","slug":"xsim-the-extreme-scale-simulator","status":"publish","type":"page","link":"https:\/\/www.christian-engelmann.info\/?page_id=433","title":{"rendered":"xSim: The Extreme-scale Simulator"},"content":{"rendered":"<table style=\"border:5pt solid grey; padding:10pt;\">\n<tr style=\"border:0pt; padding:0pt;\">\n<td style=\"border:0pt; padding:0pt; text-align:left;\"><i><b>Summary:<\/b> The Extreme-scale Simulator (xSim) runs native high-performance computing applications with millions of concurrent execution threads in a controlled environment, while observing performance and resilience in a simulated extreme-scale system for application-architecture co-design. It is able to simulate a supercomputer with 134,217,728 (2<sup>27<\/sup>) processes using a 960-core Linux cluster. It also offers process failure and soft error injection to study propagation, detection, notification and mitigation.<\/i><\/td>\n<\/tr>\n<\/table>\n<p>The path to exascale high-performance computing (HPC) poses several challenges related to power, performance, resilience, productivity, programmability, data movement, and data management. Investigating the performance and resilience of parallel applications at scale on future architectures and the performance and resilience impact of different architecture choices is an important component of HPC hardware\/software co-design. Without having access to future architectures at scale, simulation approaches provide an alternative for estimating parallel application performance and resilience on potential architecture choices. As highly accurate simulations are extremely slow and less scalable, different solution paths exist to trade-off simulation accuracy in order to gain simulation performance and scalability.<\/p>\n<p>The Extreme-scale Simulator (xSim) is a performance investigation toolkit that permits running native HPC applications or proxy applications in a controlled environment with millions of concurrent execution threads, while observing application performance and resilience in a simulated extreme-scale system for hardware\/software co-design. Using a lightweight parallel discrete event simulation (PDES), xSim executes a Message Passing Interface (MPI) application on a much smaller system in a highly oversubscribed fashion with a virtual wall clock time, such that performance data can be extracted based on a processor and a network model with an appropriate simulation scalability\/accuracy trade-off (Figure 1). xSim is designed like a traditional performance tool, as an interposition library that sits between the MPI application and the MPI library, using the MPI profiling interface (Figure 2). It has been run up to 134,217,728 (2^27) communicating MPI ranks using a 960-core Linux cluster (see Figure 3 for 2^24 results).<\/p>\n<p>xSim also permits the injection of MPI process failures, the propagation\/detection\/notification of such failures within the simulation, and their handling within the simulation using application-level checkpoint\/restart. These capabilities enable the observation of application behavior and performance under failure within a simulated future-generation HPC system using the most common fault handling technique. Another feature provides <a href=\"http:\/\/fault-tolerance.org\/ulfm\/ulfm-specification\" target=\"fault-tolerance.org_ulfm_ulfm-specification\">user-level failure mitigation (ULFM)<\/a> extensions at the simulated MPI layer to support algorithm-based fault tolerance (ABFT). This permits investigating performance under failure and failure handling of ABFT solutions using the fault-tolerant MPI extensions proposed by the <a href=\"http:\/\/meetings.mpi-forum.org\" target=\"meetings.mpi-forum.org\">MPI Fault Tolerance Working Group<\/a>. xSim is the very first performance tool that supports ULFM and ABFT.<\/p>\n<p>xSim also permits the injection of bit flip faults at specific of injection location(s) and fault activation time(s), while supporting a significant degree of configurability of the fault type. As radiation-induced bit flip faults are of particular concern in extreme-scale high-performance computing systems, xSim enables the development of soft-error resilient message passing applications by permitting the investigation of their correctness and performance under various fault conditions using this bit flip fault injection feature. xSim is the very first simulation-based MPI performance tool that supports both, the injection of process failures and bit flip faults.<\/p>\n<table style=\"border:0pt; padding:0pt;\">\n<tr style=\"border:0pt; padding:0pt;\">\n<td style=\"border:0pt; padding:0pt;\" width=\"40\"><\/td>\n<td style=\"border:0pt; padding:0pt; text-align:center;\">\n<img loading=\"lazy\" decoding=\"async\" src=\"images\/xsim\/architecture.png\" height=\"188\" width=\"228\" border=\"0\" vspace=\"0\"><br \/>\nFigure 1: xSim Architecture\n<\/td>\n<td style=\"border:0pt; padding:0pt;\" width=\"40\"><\/td>\n<td style=\"border:0pt; padding:0pt; text-align:center;\">\n<img decoding=\"async\" loading=\"lazy\" src=\"images\/xsim\/design.png\" height=\"188\" width=\"207\" border=\"0\" vspace=\"0\"><br \/>\nFigure 2: xSim Design\n<\/td>\n<td style=\"border:0pt; padding:0pt;\" width=\"40\"><\/td>\n<td style=\"border:0pt; padding:0pt; text-align:center;\">\n<img decoding=\"async\" loading=\"lazy\" src=\"images\/xsim\/scaling.png\" height=\"188\" width=\"313\" border=\"0\" vspace=\"0\"><br \/>\nFigure 3: Scaling a Monte Carlo code to 2^24 MPI ranks\n<\/td>\n<td style=\"border:0pt; padding:0pt;\" width=\"40\"><\/td>\n<\/tr>\n<\/table>\n<h4>Research Projects<\/h4>\n<ul>\n<li><a href=\"?page_id=234\">2013-16: MCREX: Monte Carlo Resilient Exascale Solvers<\/a><\/li>\n<li><a href=\"?page_id=244\">2012-14: Hardware\/Software Resilience Co-Design Tools for Extreme-scale High-Performance Computing<\/a><\/li>\n<li><a href=\"?page_id=248\">2011-12: Extreme-scale Algorithms and Software Institute<\/a><\/li>\n<li><a href=\"?page_id=342\">2008-11: Scalable Algorithms for Petascale Systems with Multicore Architectures<\/a><\/li>\n<\/ul>\n<h4>Peer-reviewed Journal Publications<\/h4>\n<ol>\n<li>Christian Engelmann and Thomas Naughton. <b>A New Deadlock Resolution Protocol and Message Matching Algorithm for the Extreme-scale Simulator<\/b>. <i><a href=\"http:\/\/onlinelibrary.wiley.com\/journal\/10.1002\/(ISSN)1532-0634\" target=\"onlinelibrary.wiley.com\/journal\/10.1002\/(ISSN)1532-0634\">Concurrency and Computation: Practice and Experience<\/a><\/i>, volume 28, number 12, pages 3369-3389, August 1, 2016. <a href=\"http:\/\/www.wiley.com\" target=\"www.wiley.com\">John Wiley &#038; Sons, Inc.<\/a>. ISSN 1532-0634. DOI <a href=\"http:\/\/dx.doi.org\/10.1002\/cpe.3805\" target=\"publication\">10.1002\/cpe.3805<\/a>. <a href=\"javascript:showAbstract('Investigating the performance of parallel applications at scale on future high-performance computing (HPC) architectures and the performance impact of different HPC architecture choices is an important component of HPC hardware\/software co-design. The Extreme-scale Simulator (xSim) is a simulation toolkit for investigating the performance of parallel applications at scale. xSim scales to millions of simulated Message Passing Interface (MPI) processes. The xSim toolkit strives to limit simulation overheads in order to maintain performance and productivity criteria. This paper documents two improvements to xSim: (1) a new deadlock resolution protocol to reduce the parallel discrete event simulation overhead, and (2) a new simulated MPI message matching algorithm to reduce the oversubscription management cost. These enhancements resulted in significant performance improvements. The simulation overhead for running the NAS Parallel Benchmark suite dropped from 1,020% to 238% for the conjugate gradient (CG) benchmark and 102% to 0% for the embarrassingly parallel (EP) benchmark. Additionally, the improvements were beneficial for reducing overheads in the highly accurate simulation mode of xSim, which is useful for resilience investigation studies for tracking intentional MPI process failures. In the highly accurate mode, the simulation overhead was reduced from 37,511% to 13,808% for CG and from 3,332% to 204% for EP.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann16new.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"?page_id=55#engelmann16new\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann. <b>Scaling To A Million Cores And Beyond: Using Light-Weight Simulation to Understand The Challenges Ahead On The Road To Exascale<\/b>. <i><a href=\"http:\/\/www.elsevier.com\/locate\/fgcs\" target=\"www.elsevier.com\/locate\/fgcs\">Future Generation Computer Systems (FGCS)<\/a><\/i>, volume 30, number 0, pages 59-65, January 1, 2014. <a href=\"http:\/\/www.elsevier.com\" target=\"www.elsevier.com\">Elsevier B.V, Amsterdam, The Netherlands<\/a>. ISSN 0167-739X. DOI <a href=\"http:\/\/dx.doi.org\/10.1016\/j.future.2013.04.014\" target=\"publication\">10.1016\/j.future.2013.04.014<\/a>. <a href=\"javascript:showAbstract('As supercomputers scale to 1,000 PFlop\/s over the next decade, investigating the performance of parallel applications at scale on future architectures and the performance impact of different architecture choices for high-performance computing (HPC) hardware\/software co-design is crucial. This paper summarizes recent efforts in designing and implementing a novel HPC hardware\/software co-design toolkit. The presented Extreme-scale Simulator (xSim) permits running an HPC application in a controlled environment with millions of concurrent execution threads while observing its performance in a simulated extreme-scale HPC system using architectural models and virtual timing. This paper demonstrates the capabilities and usefulness of the xSim performance investigation toolkit, such as its scalability to 2^27 simulated Message Passing Interface (MPI) ranks on 960 real processor cores, the capability to evaluate the performance of different MPI collective communication algorithms, and the ability to evaluate the performance of a basic Monte Carlo application with different architectural parameters.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann13scaling.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"?page_id=55#engelmann13scaling\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<\/ol>\n<h4>Peer-reviewed Conference Publications<\/h4>\n<ol>\n<li>Mahesh Lagadapati, Frank Mueller, and Christian Engelmann. <b>Benchmark Generation and Simulation at Extreme Scale<\/b>. In <i>Proceedings of the <a href=\"http:\/\/ds-rt.com\/2016\" target=\"ds-rt.com\/2016\">20th IEEE\/ACM International Symposium on Distributed Simulation and Real Time Applications (DS-RT) 2016<\/a><\/i>, pages 9-18, London, UK, September 21-23, 2016. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-1-5090-3506-9. ISSN 1550-6525. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/DS-RT.2016.18\" target=\"publication\">10.1109\/DS-RT.2016.18<\/a>. Acceptance rate 42.0% (21\/50). Best paper candidate. <a href=\"javascript:showAbstract('The path to extreme scale high-performance computing (HPC) poses several challenges related to power, performance, resilience, productivity, programmability, data movement, and data management. Investigating the performance of parallel applications at scale on future architectures and the performance impact of different architectural choices is an important component of HPC hardware\/software co-design. Simulations using models of future HPC systems and communication traces from applications running on existing HPC systems can offer an insight into the performance of future architectures. This work targets technology developed for scalable application tracing of communication events. It focuses on extreme-scale simulation of HPC applications and their communication behavior via lightweight parallel discrete event simulation for performance estimation and evaluation. Instead of simply replaying a trace within a simulator, this work promotes the generation of a benchmark from traces. This benchmark is subsequently exposed to simulation using models to reflect the performance characteristics of future-generation HPC systems. This technique provides a number of benefits, such as eliminating the data intensive trace replay and enabling simulations at different scales. The presented work features novel software co-design aspects, combining the ScalaTrace tool to generate scalable trace files, the ScalaBenchGen tool to generate the benchmark, and the xSim tool to assess the benchmark characteristics within a simulator.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/lagadapati16benchmark.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/lagadapati16benchmark.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#lagadapati16benchmark\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann and Thomas Naughton. <b>Supporting the Development of Soft-Error Resilient Message Passing Applications using Simulation<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.iasted.org\/conferences\/home-795.html\" target=\"www.iasted.org\/conferences\/home-795.html\">13th IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN) 2016<\/a><\/i>, Innsbruck, Austria, February 15-16, 2016. <a href=\"http:\/\/www.actapress.com\" target=\"www.actapress.com\">ACTA Press, Calgary, AB, Canada<\/a>. ISBN 978-0-88986-979-0. DOI <a href=\"http:\/\/dx.doi.org\/10.2316\/P.2016.834-005\" target=\"publication\">10.2316\/P.2016.834-005<\/a>. <a href=\"javascript:showAbstract('Radiation-induced bit flip faults are of particular concern in extreme-scale high-performance computing systems. This paper presents a simulation-based tool that enables the development of soft-error resilient message passing applications by permitting the investigation of their correctness and performance under various fault conditions. The documented extensions to the Extreme-scale Simulator (xSim) enable the injection of bit flip faults at specific of injection location(s) and fault activation time(s), while supporting a significant degree of configurability of the fault type. Experiments show that the simulation overhead with the new feature is ~2,325% for serial execution and ~1,730% at 128 MPI processes, both with very fine-grain fault injection. Fault injection experiments demonstrate the usefulness of the new feature by injecting bit flips in the input and output matrices of a matrix-matrix multiply application, revealing vulnerability of data structures, masking and error propagation. xSim is the very first simulation-based MPI performance tool that supports both, the injection of process failures and bit flip faults.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann16supporting.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/engelmann16supporting.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann16supporting\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann and Thomas Naughton. <b>A Network Contention Model for the Extreme-scale Simulator<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.iasted.org\/conferences\/home-826.html\" target=\"www.iasted.org\/conferences\/home-826.html\">34th IASTED International Conference on Modelling, Identification and Control (MIC) 2015<\/a><\/i>, Innsbruck, Austria, February 17-18, 2015. <a href=\"http:\/\/www.actapress.com\" target=\"www.actapress.com\">ACTA Press, Calgary, AB, Canada<\/a>. ISBN 978-0-88986-975-2. DOI <a href=\"http:\/\/dx.doi.org\/10.2316\/P.2015.826-043\" target=\"publication\">10.2316\/P.2015.826-043<\/a>. <a href=\"javascript:showAbstract('The Extreme-scale Simulator (xSim) is a performance investigation toolkit for high-performance computing (HPC) hardware\/software co-design. It permits running a HPC application with millions of concurrent execution threads, while observing its performance in a simulated extreme-scale system. This paper details a newly developed network modeling feature for xSim, eliminating the shortcomings of the existing network modeling capabilities. The approach takes a different path for implementing network contention and bandwidth capacity modeling using a less synchronous and accurate enough model design. With the new network modeling feature, xSim is able to simulate on-chip and on-node networks with reasonable accuracy and overheads.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann15network.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/engelmann15network.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann15network\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann and Thomas Naughton. <b>Improving the Performance of the Extreme-scale Simulator<\/b>. In <i>Proceedings of the <a href=\"http:\/\/ds-rt.com\/2014\" target=\"ds-rt.com\/2014\">18th IEEE\/ACM International Symposium on Distributed Simulation and Real Time Applications (DS-RT) 2014<\/a><\/i>, pages 198-207, Toulouse, France, October 1-3, 2014. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-1-4799-6143-6. ISSN 1550-6525. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/DS-RT.2014.32\" target=\"publication\">10.1109\/DS-RT.2014.32<\/a>. Best paper candidate. <a href=\"javascript:showAbstract('Investigating the performance of parallel applications at scale on future high-performance computing (HPC) architectures and the performance impact of different architecture choices is an important component of HPC hardware\/software co-design. The Extreme-scale Simulator (xSim) is a simulation-based toolkit for investigating the performance of parallel applications at scale. xSim scales to millions of simulated Message Passing Interface (MPI) processes. The overhead introduced by a simulation tool is an important performance and productivity aspect. This paper documents two improvements to xSim: (1) a new deadlock resolution protocol to reduce the parallel discrete event simulation management overhead and (2) a new simulated MPI message matching algorithm to reduce the oversubscription management overhead. The results clearly show a significant performance improvement, such as by reducing the simulation overhead for running the NAS Parallel Benchmark suite inside the simulator  from 1,020% to 238% for the conjugate gradient (CG) benchmark and from 102% to 0% for the embarrassingly parallel (EP) and benchmark, as well as, from 37,511% to 13,808% for CG and from 3,332% to 204% for EP with accurate process failure simulation.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann14improving.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/engelmann14improving.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann14improving\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Thomas Naughton, Christian Engelmann, Geoffroy Vall&eacute;e, and Swen B&ouml;hm. <b>Supporting the Development of Resilient Message Passing Applications using Simulation<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.pdp2014.org\" target=\"www.pdp2014.org\">22nd Euromicro International Conference on Parallel, Distributed, and network-based Processing (PDP) 2014<\/a><\/i>, pages 271-278, Turin, Italy, February 12-14, 2014. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISSN 1066-6192. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/PDP.2014.74\" target=\"publication\">10.1109\/PDP.2014.74<\/a>. Acceptance rate 32.6% (73\/224). <a href=\"javascript:showAbstract('An emerging aspect of high-performance computing (HPC) hardware\/software co-design is investigating performance under failure. The work in this paper extends the Extreme-scale Simulator (xSim), which was designed for evaluating the performance of message passing interface (MPI) applications on future HPC architectures, with fault-tolerant MPI extensions proposed by the MPI Fault Tolerance Working Group. xSim permits running MPI applications with millions of concurrent MPI ranks, while observing application performance in a simulated extreme-scale system using a lightweight parallel discrete event simulation. The newly added features offer user-level failure mitigation (ULFM) extensions at the simulated MPI layer to support algorithm-based fault tolerance (ABFT). The presented solution permits investigating performance under failure and failure handling of ABFT solutions. The newly enhanced xSim is the very first performance tool that supports ULFM and ABFT.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/naughton14supporting.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/naughton14supporting.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#naughton14supporting\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann. <b>Investigating Operating System Noise in Extreme-Scale High-Performance Computing Systems using Simulation<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.iasted.org\/conferences\/home-795.html\" target=\"www.iasted.org\/conferences\/home-795.html\">11th IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN) 2013<\/a><\/i>, Innsbruck, Austria, February 11-13, 2013. <a href=\"http:\/\/www.actapress.com\" target=\"www.actapress.com\">ACTA Press, Calgary, AB, Canada<\/a>. ISBN 978-0-88986-943-1. DOI <a href=\"http:\/\/dx.doi.org\/10.2316\/P.2013.795-010\" target=\"publication\">10.2316\/P.2013.795-010<\/a>. <a href=\"javascript:showAbstract('Hardware\/software co-design for future-generation high-performance computing (HPC) systems aims at closing the gap between the peak capabilities of the hardware and the performance realized by applications (application-architecture performance gap). Performance profiling of architectures and applications is a crucial part of this iterative process. The work in this paper focuses on operating system (OS) noise as an additional factor to be considered for co-design. It represents the first step in including OS noise in HPC hardware\/software co-design by adding a noise injection feature to an existing simulation-based co-design toolkit. It reuses an existing abstraction for OS noise with frequency (periodic recurrence) and period (duration of each occurrence) to enhance the processor model of the Extreme-scale Simulator (xSim) with synchronized and random OS noise simulation. The results demonstrate this capability by evaluating the impact of OS noise on MPI_Bcast() and MPI_Reduce() in a simulated future-generation HPC system with 2,097,152 compute nodes.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann13investigating.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/engelmann13investigating.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann13investigating\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Swen B&ouml;hm and Christian Engelmann. <b>xSim: The Extreme-Scale Simulator<\/b>. In <i>Proceedings of the <a href=\"http:\/\/hpcs11.cisedu.info\" target=\"hpcs11.cisedu.info\">International Conference on High Performance Computing and Simulation (HPCS) 2011<\/a><\/i>, pages 280-286, Istanbul, Turkey, July 4-8, 2011. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-1-61284-383-4. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/HPCSim.2011.5999835\" target=\"publication\">10.1109\/HPCSim.2011.5999835<\/a>. Acceptance rate 28.1% (48\/171). <a href=\"javascript:showAbstract('Investigating parallel application performance properties at scale is becoming an important part of high-performance computing (HPC) application development and deployment. The Extreme-scale Simulator (xSim) is a performance investigation toolkit that permits running an application in a controlled environment at extreme scale without the need for a respective extreme-scale HPC system. Using a lightweight parallel discrete event simulation, xSim executes a parallel application with a virtual wall clock time, such that performance data can be extracted based on a processor model and a network model. This paper presents significant enhancements to the xSim toolkit prototype that provide a more complete Message Passing Interface (MPI) support and improve its versatility. These enhancements include full virtual MPI group, communicator and collective communication support, and global variables support. The new capabilities are demonstrated by executing the entire NAS Parallel Benchmark suite in a simulated HPC environment.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/boehm11xsim.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/boehm11xsim.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#boehm11xsim\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<\/ol>\n<h4>Peer-reviewed Workshop Publications<\/h4>\n<ol>\n<li>Christian Engelmann and Thomas Naughton. <b>Toward a Performance\/Resilience Tool for Hardware\/Software Co-Design of High-Performance Computing Systems<\/b>. In <i>Proceedings of the <a href=\"http:\/\/icpp2013.ens-lyon.fr\" target=\"icpp2013.ens-lyon.fr\">42nd International Conference on Parallel Processing (ICPP) 2013<\/a>: <a href=\"http:\/\/www.psti-workshop.org\" target=\"www.psti-workshop.org\">4th International Workshop on Parallel Software Tools and Tool Infrastructures (PSTI)<\/a><\/i>, pages 962-971, Lyon, France, October 2, 2013. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-0-7695-5117-3. ISSN 0190-3918. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/ICPP.2013.114\" target=\"publication\">10.1109\/ICPP.2013.114<\/a>. <a href=\"javascript:showAbstract('xSim is a simulation-based performance investigation toolkit that permits running high-performance computing (HPC) applications in a controlled environment with millions of concurrent execution threads, while observing application performance in a simulated extreme-scale system for hardware\/software co-design. The presented work details newly developed features for xSim that permit the injection of MPI process failures, the propagation\/detection\/notification of such failures within the simulation, and their handling using application-level checkpoint\/restart. These new capabilities enable the observation of application behavior and performance under failure within a simulated future-generation HPC system using the most common fault handling technique.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann13toward.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/engelmann13toward.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann13toward\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Mahesh Lagadapati, Frank Mueller, and Christian Engelmann. <b>Tools for Simulation and Benchmark Generation at Exascale<\/b>. In <i>Proceedings of the <a href=\"http:\/\/tools.zih.tu-dresden.de\/2013\/\" target=\"tools.zih.tu-dresden.de\/2013\/\">7th Parallel Tools Workshop<\/a><\/i>, pages 19-24, Dresden, Germany, September 3-4, 2013. <a href=\"http:\/\/www.springer.com\" target=\"www.springer.com\">Springer Verlag, Berlin, Germany<\/a>. ISBN 978-3-319-08143-4. DOI <a href=\"http:\/\/dx.doi.org\/10.1007\/978-3-319-08144-1_2\" target=\"publication\">10.1007\/978-3-319-08144-1_2<\/a>. <a href=\"javascript:showAbstract('The path to exascale high-performance computing (HPC) poses several challenges related to power, performance, resilience, productivity, programmability, data movement, and data management. Investigating the performance of parallel applications at scale on future architectures and the performance impact of different architecture choices is an important component of HPC hardware\/software co-design. Simulations using models of future HPC systems and communication traces from applications running on existing HPC systems can offer an insight into the performance of future architectures. This work targets technology developed for scalable application tracing of communication events and memory profiles, but can be extended to other areas, such as I\/O, control flow, and data flow. It further focuses on extreme-scale simulation of millions of Message Passing Interface (MPI) ranks using a lightweight parallel discrete event simulation (PDES) toolkit for performance evaluation. Instead of simply replaying a trace within a simulation, the approach is to generate a benchmark from it and to run this benchmark within a simulation using models to reflect the performance characteristics of future-generation HPC systems. This provides a number of benefits, such as eliminating the data intensive trace replay and enabling simulations at different scales. The presented work utilizes the ScalaTrace tool to generate scalable trace files, the ScalaBenchGen tool to generate the benchmark, and the xSim tool to run the benchmark within a simulation.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/lagadapati13tools.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/lagadapati13tools.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#lagadapati13tools\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Ian S. Jones and Christian Engelmann. <b>Simulation of Large-Scale HPC Architectures<\/b>. In <i>Proceedings of the <a href=\"http:\/\/icpp2011.org\" target=\"icpp2011.org\">40th International Conference on Parallel Processing (ICPP) 2011<\/a>: <a href=\"http:\/\/www.psti-workshop.org\" target=\"www.psti-workshop.org\">2nd International Workshop on Parallel Software Tools and Tool Infrastructures (PSTI)<\/a><\/i>, pages 447-456, Taipei, Taiwan, September 13-19, 2011. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-0-7695-4511-0. ISSN 1530-2016. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/ICPPW.2011.44\" target=\"publication\">10.1109\/ICPPW.2011.44<\/a>. <a href=\"javascript:showAbstract('The Extreme-scale Simulator (xSim) is a recently developed performance investigation toolkit that permits running high-performance computing (HPC) applications in a controlled environment with millions of concurrent execution threads. It allows observing parallel application performance properties in a simulated extreme-scale HPC system to further assist in HPC hardware and application software co-design on the road toward multi-petascale and exascale computing. This paper presents a newly implemented network model for the xSim performance investigation toolkit that is capable of providing simulation support for a variety of HPC network architectures with the appropriate trade-off between simulation scalability and accuracy. The taken approach focuses on a scalable distributed solution with latency and bandwidth restrictions for the simulated network. Different network architectures, such as star, ring, mesh, torus, twisted torus and tree, as well as hierarchical combinations, such as to simulate network-on-chip and network-on-node, are supported. Network traffic congestion modeling is omitted to gain simulation scalability by reducing simulation accuracy.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/jones11simulation.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/jones11simulation.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#jones11simulation\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann and Frank Lauer. <b>Facilitating Co-Design for Extreme-Scale Systems Through Lightweight Simulation<\/b>. In <i>Proceedings of the <a href=\"http:\/\/www.cluster2010.org\" target=\"www.cluster2010.org\">12th IEEE International Conference on Cluster Computing (Cluster) 2010<\/a>: <a href=\"http:\/\/www2.wmin.ac.uk\/getovv\/aacec10.html\" target=\"www2.wmin.ac.uk\/getovv\/aacec10.html\">1st Workshop on Application\/Architecture Co-design for Extreme-scale Computing (AACEC)<\/a><\/i>, pages 1-8, Hersonissos, Crete, Greece, September 20-24, 2010. <a href=\"http:\/\/www.computer.org\" target=\"www.computer.org\">IEEE Computer Society, Los Alamitos, CA, USA<\/a>. ISBN 978-1-4244-8395-2. DOI <a href=\"http:\/\/dx.doi.org\/10.1109\/CLUSTERWKSP.2010.5613113\" target=\"publication\">10.1109\/CLUSTERWKSP.2010.5613113<\/a>. <a href=\"javascript:showAbstract('This work focuses on tools for investigating algorithm performance at extreme scale with millions of concurrent threads and for evaluating the impact of future architecture choices to facilitate the co-design of high-performance computing (HPC) architectures and applications. The approach focuses on lightweight simulation of extreme-scale HPC systems with the needed amount of accuracy. The prototype presented in this paper is able to provide this capability using a parallel discrete event simulation (PDES), such that a Message Passing Interface (MPI) application can be executed at extreme scale, and its performance properties can be evaluated. The results of an initial prototype are encouraging as a simple hello world MPI program could be scaled up to 1,048,576 virtual MPI processes on a four-node cluster, and the performance properties of two MPI programs could be evaluated at up to 1,024 and 16,384 virtual MPI processes on the same system.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann10facilitating.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/engelmann10facilitating.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann10facilitating\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<\/ol>\n<h4>White Papers<\/h4>\n<ol>\n<li>Christian Engelmann and Thomas Naughton. <b>A Hardware\/Software Performance\/Resilience\/Power Co-Design Tool for Extreme-scale Computing<\/b>. <i>White paper accepted at the U.S. Department of Energy&#39;s <a href=\"http:\/\/hpc.pnl.gov\/modsim\/2013\" target=\"hpc.pnl.gov\/modsim\/2013\">Workshop on Modeling &#038; Simulation of Exascale Systems &#038; Applications (ModSim) 2013<\/a><\/i>, September 18-19, 2013. <a href=\"javascript:showAbstract('xSim is a simulation-based performance investigation toolkit that permits running high-performance computing (HPC) applications in a controlled environment with millions of concurrent execution threads, while observing application performance in a simulated extreme-scale system for hardware\/software co-design. The presented work details newly developed features for xSim that permit the injection of MPI process failures, the propagation\/detection\/notification of such failures within the simulation, and their handling using application-level checkpoint\/restart. The newly added features also offer user-level failure mitigation (ULFM) extensions at the simulated MPI layer to support algorithm-based fault tolerance (ABFT). The presented solution permits investigating performance under failure and failure handling of checkpoint\/restart and ABFT solutions. The newly enhanced xSim is the very first performance tool that supports these capabilities.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann13hardware.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/engelmann13hardware.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann13hardware\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann and Thomas Naughton. <b>A Performance\/Resilience\/Power Co-design Tool for Extreme-scale High-Performance Computing<\/b>. <i>White paper accepted at the U.S. Department of Energy&#39;s <a href=\"http:\/\/hpc.pnl.gov\/modsim\/2012\" target=\"hpc.pnl.gov\/modsim\/2012\">Workshop on Modeling &#038; Simulation of Exascale Systems &#038; Applications (ModSim) 2012<\/a><\/i>, August 9-10, 2012. <a href=\"javascript:showAbstract('Performance, resilience and power consumption are key HPC system design factors that are highly interde-pendent. To enable extreme-scale computing it is essential to perform HPC hardware\/software co-design that identifies the cost\/benefit trade-off between these design factors for potential future architecture choices. The proposed research and development aims at developing an HPC hardware\/software co-design toolkit for evaluating the resilience\/power\/performance cost\/benefit trade-off of future architecture choices. The approach focuses on extending a simulation-based performance investigation toolkit with advanced resilience and power modeling and simulation features, such as (i) fault injection mechanisms, (ii) fault propagation, isolation, and detection models, (i) fault avoidance, masking, and recovery simulation, and (iv) power consumption models.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann12performance.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"?page_id=55#engelmann12performance\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<\/ol>\n<h4>Talks and Lectures<\/h4>\n<ol>\n<li>Christian Engelmann. <b>Resilience Challenges and Solutions for Extreme-Scale Supercomputing<\/b>. Invited talk at the <a href=\"http:\/\/www.usna.edu\" target=\"www.usna.edu\">United  States Naval Academy<\/a>, Annapolis, MD, USA, February 18, 2016. <a href=\"javascript:showAbstract('The path to exascale computing poses several research challenges related to power, performance, resilience, productivity, programmability, data movement, and data management. Resilience, i.e., providing efficiency and correctness in the presence of faults, is one of the most important exascale computer science challenges as systems scale up in component count (100,000-1,000,000 nodes with 1,000-10,000 cores per node by 2022) and component reliability decreases (7 nm technology with near-threshold voltage operation by 2022). This talk provides an overview of recent and ongoing resilience research and development activities at Oak Ridge National Laboratory in advanced checkpoint storage architectures, process-level incremental checkpoint\/restart, proactive fault tolerance using prediction-triggered process or virtual machine migration, MPI process-level software redundancy, and soft-error injection tools to study the vulnerability of science applications.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann16resilience2.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann16resilience2\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann. <b>Resilience Challenges and Solutions for Extreme-Scale Supercomputing<\/b>. Invited talk at the  19th Workshop on Distributed Supercomputing (SOS)   2015, Park City, UT, USA, March 2-5, 2015. <a href=\"javascript:showAbstract('The path to exascale computing poses several research challenges related to power, performance, resilience, productivity, programmability, data movement, and data management. Resilience, i.e., providing efficiency and correctness in the presence of faults, is one of the most important exascale computer science challenges as systems scale up in component count (100,000-1,000,000 nodes with 1,000-10,000 cores per node by 2022) and component reliability decreases (7 nm technology with near-threshold voltage operation by 2022). This talk provides an overview of recent and ongoing resilience research and development activities at Oak Ridge National Laboratory in advanced checkpoint storage architectures, process-level incremental checkpoint\/restart, proactive fault tolerance using prediction-triggered process or virtual machine migration, MPI process-level software redundancy, and soft-error injection tools to study the vulnerability of science applications.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann15resilience.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann15resilience\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann. <b>xSim: The Extreme-scale Simulator<\/b>. Seminar at the <a href=\"http:\/\/www.lrz-muenchen.de\" target=\"www.lrz-muenchen.de\">Leibniz Rechenzentrum (LRZ)<\/a>, Garching, Germany, February 23, 2015. <a href=\"javascript:showAbstract('The path to exascale high-performance computing (HPC) poses several challenges related to power, performance, and resilience. Investigating the performance and resilience of parallel applications at scale on future architectures and the performance and resilience impact of different architecture choices is an important component of HPC hardware\/software co-design. Without having access to future architectures at scale, simulation provides an alternative. The Extreme-scale Simulator (xSim) is a performance investigation toolkit that permits running applications in a controlled environment with millions of concurrent execution threads, while observing performance and resilience in a simulated extreme-scale system. Using a lightweight parallel discrete event simulation, xSim executes a Message Passing Interface (MPI) application on a much smaller system in a highly oversubscribed fashion with a virtual wall clock time, such that performance data can be extracted based on a processor and a network model. xSim is designed like a traditional performance tool, as an interposition library that sits between the MPI application and the MPI library, using the MPI profiling interface. It has been run up to 134,217,728 (2^27) MPI ranks using a 960-core Linux cluster. xSim also permits the injection of MPI process failures, the propagation\/detection\/notification of such failures within the simulation, and their handling within the simulation using application-level checkpoint\/restart. Another feature provides user-level failure mitigation (ULFM) extensions at the simulated MPI layer to support algorithm-based fault tolerance (ABFT). xSim is the very first performance tool that supports ULFM and ABFT.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann15xsim.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann15xsim\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann. <b>Supporting the Development of Resilient Message Passing Applications using Simulation<\/b>. Invited talk at the <a href=\"http:\/\/www.dagstuhl.de\/en\/program\/calendar\/semhp\/?semnr=14402\" target=\"www.dagstuhl.de\/en\/program\/calendar\/semhp\/?semnr=14402\">Dagstuhl Seminar on Resilience in Exascale Computing<\/a>, Schloss Dagstuhl, Wadern, Germany, September 28 &#8211; October 1, 2014. <a href=\"javascript:showAbstract('An emerging aspect of high-performance computing (HPC) hardware\/software co-design is investigating performance under failure. The presented work extends the Extreme-scale Simulator (xSim), which was designed for evaluating the performance of message passing interface (MPI) applications on future HPC architectures, with fault-tolerant MPI extensions proposed by the MPI Fault Tolerance Working Group. xSim permits running MPI applications with millions of concurrent MPI ranks, while observing application performance in a simulated extreme-scale system using a lightweight parallel discrete event simulation. The newly added features offer user-level failure mitigation (ULFM) extensions at the simulated MPI layer to support algorithm-based fault tolerance (ABFT). The presented solution permits investigating performance under failure and failure handling of ABFT solutions. The newly enhanced xSim is the very first performance tool that supports ULFM and ABFT.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann14supporting.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann14supporting\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann. <b>Resilience Challenges and Solutions for Extreme-Scale Supercomputing<\/b>. Invited talk at the Technical University of Dresden,  Dresden, Germany, September 3, 2013. <a href=\"javascript:showAbstract('With the recent deployment of the 18 PFlop\/s Titan supercomputer and the exascale roadmap targeting 100, 300, and eventually 1,000 PFlop\/s by 2022, Oak Ridge National Laboratory is at the forefront of scientific capability computing. The path to exascale computing poses several research challenges related to power, performance, resilience, productivity, programmability, data movement, and data management. Resilience, i.e., providing efficiency and correctness in the presence of faults, is one of the most important exascale computer science challenges as systems scale up in component count (100,000-1,000,000 nodes with 1,000-10,000 cores per node by 2022) and component reliability decreases (7 nm technology with near-threshold voltage operation by 2022). This talk provides an overview of recent and ongoing resilience research and development activities at Oak Ridge National Laboratory in advanced checkpoint storage architectures, process-level incremental checkpoint\/restart, proactive fault tolerance using prediction-triggered process or virtual machine migration, MPI process-level software redundancy, and soft-error injection tools to study the vulnerability of science applications and of CMOS logic in processors and memory.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann13resilience.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann13resilience\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann. <b>Fault Tolerance Session<\/b>. Invited talk at the  <a href=\"http:\/\/www.aanmelder.nl\/exachallenge\" target=\"www.aanmelder.nl\/exachallenge\">The ExaChallenge Symposium<\/a>, Dublin, Ireland, October 16-17, 2012. <a href=\"publications\/engelmann12fault.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann12fault\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann. <b>Resilience and Hardware\/Software Co-design for Extreme-Scale Supercomputing<\/b>. Seminar at the <a href=\"http:\/\/www.bsc.es\" target=\"www.bsc.es\">Barcelona Supercomputing Center<\/a>, Barcelona, Spain, July 27, 2011. <a href=\"javascript:showAbstract('Oak Ridge National Laboratory (ORNL) provides the most powerful high-performance computing (HPC) resources in the world for open scientific research. Jaguar, a 224,162-core Cray XT5 with a LINPACK performance of 1.759 PFlop\/s, for example, is the world&amp;#39;s 3rd fastest supercomputer. 80% of its resources are allocated through a reviewed process to address the most challenging scientific problems in climate modeling, renewable energy, materials science, fusion and other areas. ORNL's Computer Science and Mathematics Division performs computer science and mathematics research to increase supercomputer efficiency and application scientist productivity while accelerating time to solution for scientific breakthroughs. This talk details recent research advancements at ORNL in two areas: (1) resilience and (2) hardware\/software co-design for extreme-scale supercomputing. Both are essential on the road toward exa-scale HPC systems with millions-to-billions of cores. Due to the expected drastic increase in scale, the corresponding decrease in system mean-time to interrupt warrants a rethinking of the traditional checkpoint\/restart approach for HPC resilience. New concepts discussed in this talk range from preventative measures, such as task migration based on fault prediction, to more aggressive fault masking, such as various levels of redundancy. Further, the expected drastic increase in task parallelism requires redesigning algorithms to avoid the consequences of Amdahl's law at extreme scale. As million-way task parallel systems don't exist yet, this talk discusses a lightweight system simulation approach for performance estimation of algorithms at scale.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann11resilience.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann11resilience\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann. <b>Beyond Application-Level Checkpoint\/Restart &#8211; Advanced Software Approaches for Fault Resilience<\/b>. Talk at the <a href=\"http:\/\/www.speedup.ch\/workshops\/w39_2010.html\" target=\"www.speedup.ch\/workshops\/w39_2010.html\">39th SPEEDUP Workshop on High Performance Computing<\/a>, Zurich, Switzerland, September 6, 2010. <a href=\"publications\/engelmann10beyond.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann10beyond\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann and Stephen L. Scott. <b>HPC System Software Research at Oak Ridge National Laboratory<\/b>. Seminar at the <a href=\"http:\/\/www.lrz-muenchen.de\" target=\"www.lrz-muenchen.de\">Leibniz Rechenzentrum (LRZ)<\/a>, Garching, Germany, February 22, 2010. <a href=\"javascript:showAbstract('Oak Ridge National Laboratory (ORNL) is the largest energy laboratory in the United States. Its National Center for Computational Sciences (NCCS) provides the most powerful computing resources in the world for open scientific research. Jaguar, a Cray XT5 system at NCCS, is the fastest supercomputer in the world. It recently ranked #1 in the Top 500 List of Supercomputer Sites with a maximal LINPACK benchmark performance of 1.759 PFlop\/s and a theoretical peak performance of 2.331 PFlop\/s, where 1 PFlop\/s is 10^15 Floating Point Operations Per Second. Annually, 80 percent of Jaguar&amp;#39;s resources are allocated through the U.S Department of Energy's Innovative and Novel Computational Impact on Theory and Experiment (INCITE) program, a competitively selected, peer reviewed process open to researchers from universities, industry, government and non-profit organizations. These allocations address some of the most challenging scientific problems in areas such as climate modeling, renewable energy, materials science, fusion and combustion. In conjunction with NCCS, the Computer Science and Mathematics Division at ORNL performs basic and applied research in HPC, mathematics, and intelligent systems. This talk gives a summary of the HPC research and development in system software performed at ORNL, including resilience at extreme scale and virtualization technologies in HPC. Specifically, this talk will focus on advanced resilience technologies, such as migration of computation away from components that are about to fail and on management and customization of virtualized environments.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/engelmann10hpc.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann10hpc\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Christian Engelmann. <b>JCAS &#8211; IAA Simulation Efforts at Oak Ridge National Laboratory<\/b>. Invited talk at the <a href=\"http:\/\/www.cs.sandia.gov\/CSRI\/Workshops\/2009\/IAA\" target=\"www.cs.sandia.gov\/CSRI\/Workshops\/2009\/IAA\">IAA Workshop on HPC Architectural Simulation (HPCAS)<\/a>, Boulder, CO, USA, September 1-2, 2009. <a href=\"publications\/engelmann09jcas.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#engelmann09jcas\"><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<\/ol>\n<h4>Co-advised Theses<\/h4>\n<ol>\n<li>Ian S. Jones. <b>Simulation of Large Scale Architectures on High Performance Computers<\/b>. Master&#8217;s thesis, <a href=\"http:\/\/www.cs.reading.ac.uk\" target=\"www.cs.reading.ac.uk\">Department of Computer Science<\/a>, <a href=\"http:\/\/www.reading.ac.uk\" target=\"www.reading.ac.uk\">University of Reading<\/a>, UK, October 22, 2010. Thesis research performed at Oak Ridge National Laboratory. Advisors: Prof. Vassil N. Alexandrov (University of Reading); Christian Engelmann (Oak Ridge National Laboratory); George Bosilca (University of Tennessee, Knoxville). <a href=\"javascript:showAbstract('Powerful supercomputers often need to be simulated for the purposes of testing the scalability of various applications. This thesis endeavours to further develop the existing simulator, XSIM, and implement the functionality to simulate real-world networks and the latency which might be encountered by messages travelling through that network. The upgraded simulator will then be tested at the Oak Ridge National Laboratory. The work completed herein should provide a solid foundation for further improvements to XSIM; it simulates a variety of basic network topologies, calculating the shortest path for any given message and generates a transmission time.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/jones10simulation.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/jones10simulation.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#jones10simulation\" ><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<li>Frank Lauer. <b>Simulation of Advanced Large-Scale HPC Architectures<\/b>. Master&#8217;s thesis, <a href=\"http:\/\/www.cs.reading.ac.uk\" target=\"www.cs.reading.ac.uk\">Department of Computer Science<\/a>, <a href=\"http:\/\/www.reading.ac.uk\" target=\"www.reading.ac.uk\">University of Reading<\/a>, UK, March 12, 2010. Thesis research performed at Oak Ridge National Laboratory. Advisors: Prof. Vassil N. Alexandrov (University of Reading); Christian Engelmann (Oak Ridge National Laboratory); George Bosilca (University of Tennessee, Knoxville). <a href=\"javascript:showAbstract('The rapid development of massive parallel systems in the high- performance computing (HPC) area requires efficient scalability of applications. The next generation&amp;#39;s design of supercomputers is today not certain in terms of what will be the computational, memory and I\/O capabilities. However it is most certain that they become even more parallel. Getting the most performance from these machines in not only a matter of hardware, it is also an issue of programming design. Therefore, it has to be a co-development. However, how to test algorithm's on machines which are not existing today. To address the programming issues in terms of scalability and fault tolerance for the next generation, this projects aim is to design and develop a simulator based on parallel discrete event simulation (PDES) for applications using MPI communication. Some of the fastest supercomputers in the world already interconnecting &amp;#36;10^5 cores together to catch up the simulator will be able to simulate at least 10^7 virtual processes.');\"><img decoding=\"async\" src=\"images\/txt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Abstract\"><\/a> <a href=\"publications\/lauer10simulation.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/pdf.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Publication\"><\/a> <a href=\"publications\/lauer10simulation.ppt.pdf\" target=\"publication\"><img decoding=\"async\" src=\"images\/ppt.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"Presentation\"><\/a> <a href=\"?page_id=55#lauer10simulation\" ><img decoding=\"async\" src=\"images\/bib.gif\" border=\"0\" style=\"border-style:none\" height=\"10pt\" alt=\"BibTeX Citation\"><\/a><\/li>\n<\/ol>\n<p><em><small>Symbols: <img decoding=\"async\" style=\"border-style: none;\" src=\"images\/txt.gif\" border=\"0\" alt=\"Abstract\" height=\"10pt\"> Abstract, <img decoding=\"async\" style=\"border-style: none;\" src=\"images\/pdf.gif\" border=\"0\" alt=\"Publication\" height=\"10pt\"> Publication, <img decoding=\"async\" style=\"border-style: none;\" src=\"images\/ppt.gif\" border=\"0\" alt=\"Presentation\" height=\"10pt\"> Presentation, <img decoding=\"async\" style=\"border-style: none;\" src=\"images\/bib.gif\" border=\"0\" alt=\"BibTeX Citation\" height=\"10pt\"> BibTeX Citation<\/small><\/em><\/p>\n<p><script language=\"JavaScript\">\nfunction showAbstract (text) {\n  var width  = 400;\n  var height = 400;\n  var left   = (screen.width  - width ) \/ 2;\n  var top    = (screen.height - height) \/ 2;\n  var win    = window.open('',\n                           'Abstract',\n                           'width='  + width  + ', ' + \n                           'height=' + height + ', ' +\n                           'left='   + left   + ', ' +\n                           'top='    + top    + ', ' +\n                           'toolbar=no, '     +\n                           'location=no, '    +\n                           'directories=no, ' +\n                           'status=no, '      +\n                           'menubar=no, '     +\n                           'copyhistory=no, ' +\n                           'scrollbars=yes, ' +\n                           'resizable=yes')\n  win.document.write(text);\n  win.document.close();\n}\n<\/script><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Summary: The Extreme-scale Simulator (xSim) runs native high-performance computing applications with millions of concurrent execution threads in a controlled environment, while observing performance and resilience in a simulated extreme-scale system for application-architecture co-design. It is able to simulate a supercomputer with 134,217,728 (227) processes using a 960-core Linux cluster. It also offers process failure and&hellip;&nbsp;<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":430,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"neve_meta_sidebar":"","neve_meta_container":"","neve_meta_enable_content_width":"off","neve_meta_content_width":100,"neve_meta_title_alignment":"","neve_meta_author_avatar":"","neve_post_elements_order":"","neve_meta_disable_header":"","neve_meta_disable_footer":"","neve_meta_disable_title":"","footnotes":""},"class_list":["post-433","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.christian-engelmann.info\/index.php?rest_route=\/wp\/v2\/pages\/433","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.christian-engelmann.info\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.christian-engelmann.info\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.christian-engelmann.info\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.christian-engelmann.info\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=433"}],"version-history":[{"count":7,"href":"https:\/\/www.christian-engelmann.info\/index.php?rest_route=\/wp\/v2\/pages\/433\/revisions"}],"predecessor-version":[{"id":1227,"href":"https:\/\/www.christian-engelmann.info\/index.php?rest_route=\/wp\/v2\/pages\/433\/revisions\/1227"}],"up":[{"embeddable":true,"href":"https:\/\/www.christian-engelmann.info\/index.php?rest_route=\/wp\/v2\/pages\/430"}],"wp:attachment":[{"href":"https:\/\/www.christian-engelmann.info\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=433"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}